|
Details, datasheet, quote on part number:NJU8725V
| |
| Part: | NJU8725V |
| Category: | Multimedia => Audio => Amplifiers => Power Amplifiers => Class D Amplifier |
| Description: | Class D Amplifier For Digital Audio |
| Company: | NJR Corporation |
| Datasheet: | Download NJU8725V datasheet File size : 153 kB |
| Request For quote: | Find where to buy NJU8725V
|
| |
Datasheet text preview:
NJU8725
PRELIMINARY
CLASS D AMPLIFIER FOR DIGITAL AUDIO
! GENERAL DESCRIPTION
The NJU8725 is an 800mW-output class D th Amplifier featuring 6 modulation. It includes Digital Attenuator, Mute, and De-emphasis circuits. It converts digital source input to PWM signal output which is converted to analog signal with simple external LC low-pass filter. The NJU8725 realizes very high power-efficiency by class D operation. Therefore, it is suitable for battery-powered applications and others.
! PACKAGE OUTLINE
NJU8725V
! FEATURES
# # # # # # # # # # # # #
! PIN CONFIGURATION
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 F0/DATA F1/REQ F2/SCK DIN VDDR O U T RP VSSR O U T RN VDDR LRCK BCK MCK
Stereo BTL Power Amplifier Sixth-order 32fS Over Sampling & PWM VDD Internal 8fS Over Sampling Digital Filter STBY Sampling Frequency : 96kHz (Max.) TEST De-Emphasis : 32kHz, 44.1kHz, 48kHz MUTE System Clock : 256fS VDDL Digital Processing : Attenuator 107step, LOG Curve : Mute OUTLP Digital Audio Interface : 16bit, 18bit VSSL 2 : I S, LSB Justified, MSB Justified OUTLN Short Circuit Protection VDDL Operating Voltage : 3.0 to 3.6V Driving Voltage : VDD to 5.25V MODE C-MOS Technology RST Package Outline : SSOP24 VSS
! BLOCK DIAGRAM
VDD VSS RST MCK LRCK BCK DIN MUTE STBY MODE F0/DATA F1/REQ F2/SCK Serial Audio Data Interface 8fS Over Sampling Digital Filter 32fS 6 & PWM
th
Power On Reset Circuit Synchronization Circuit
Short Circuit Protection VDDL OUTLP VSSL VDDL OUTLN VSSL VDDR O U T RP
System Control
VSSR VDDR O U T RN VSSR
-1-
NJU8725
! TERMINAL DESCRIPTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SYMBOL VDD STBY TEST MUTE VDDL OUTLP VSSL OUTLN VDDL MODE RST VSS MCK BCK LRCK VDDR OUTRN VSSR OUTRP VDDR DIN F2/SCK I/O - I I I - O - O - I I - I I I - O - O - I I FUNCTION Logic Power Supply, VDD=3.3V Standby Control Terminal Low : Standby ON High : Standby OFF Manufacturer Testing Terminal Normally connect to GND. Mute Control Terminal Low : Mute ON High : Mute OFF Lch Power Supply, VDDL=VDD to 5.0V Lch Positive Output Terminal Lch Power GND, VSSL=0V Lch Negative Output Terminal Lch Power Supply, VDDL=VDD to 5.0V Control Mode selection Terminal Low : Parallel Control Mode High : Serial Control Mode Reset Terminal Low : Reset ON High : Reset OFF Logic Power GND, VSS=0V Master Clock Input Terminal 256fS clock inputs this terminal. Serial Audio Data Bit Clock Input Terminal This clock must synchronize with MCK input signal. L/R Channel Clock Input Terminal This clock must synchronize with MCK input signal. Rch Power Supply, VDDR=VDD to 5.0V Rch Negative Output Terminal Rch Power GND, VSSR=0V Rch Positive Output Terminal Rch Power Supply, VDDR=VDD to 5.0V Serial Audio Data Input Terminal MODE="Low" : Serial Audio Interface Format Selection Terminal 2 MODE="High" : Control Register Data Shift Clock Input Terminal The data is fetched into the control register by rise edge of SCK signal. MODE="Low" : Serial Audio Interface Format Selection Terminal 1 MODE="High" : Control Register Data Request Input Terminal MODE="Low" : Serial Audio Interface Format Selection Terminal 0 MODE="High" : Control Register Data Input Terminal
23 24
F1/REQ F0/DATA
I I
! INPUT TERMINAL STRUCTURE
VDD
Input Terminal VSS
Inside Circuit
-2-
NJU8725
! FUNCTIONAL DESCRIPTION
(1) Signal Output PWM signals of L channel and R output from OUTLP/LN and OUTRP/RN terminals respectively. These signals are converted to analog signal by external 2nd-order or over LC filter. The output driver power supplied from VDDL, VDDR, VSSL, and VSSR are required high response power supply against voltage fluctuation like as switching regulator because Output THD is effected by power supply stability. (2) Master Clock Master Clock is 256fS clock into MCK terminal for the internal circuit operation clock. (3) Reset "L" level input over than 3ms to the RST terminal is initialization signal to initialize the internal circuit. This initialization signal is synchronized with internal clock and executes logical OR with the internal power on reset signal. This Reset signal initializes the internal function setting registers also. During initialization, the output-drivers output GND level. The reset equivalent circuit is shown bellow.
RST Power on Reset CLK (About 10kHz)
Internal Reset
D D D D D D D D
Figure 1. Reset Equivalent Circuit
(4) 8fS Over Sampling Digital Filter 8fS Over Sampling Digital Filter interpolates Audio data and decreases aliasing noise. It realizes Attenuation and De-Emphasis function by serial function control.
(5) 32fS 6 & PWM th 32fS 6 & PWM convert from Audio data of the 8fS Over Sampling Digital Filter to the 32fS one bit PWM data.
th
(6) Short Circuit Protection Short Circuit Protection protects IC with output terminal of high-impedance condition when output terminal is shorted to GND or other output terminal. The high-impedance condition is released automatically with master clock input, not released without master clock input.
-3-
|
|
