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Details, datasheet, quote on part number:NOV4431
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Datasheet text preview:
PRELIMINARY
PRODUCT BRIEF
OC-48/STM-16 Or Quad OC-12/STM-3 Channelized ATM/POS/TDM PHYSICAL LAYER IC
GENERAL DESCRIPTION
The LongBoat device is a highly integrated IC providing full-duplex mapping functions of ATM cells, ATM frames, PPP packets and TDM traffic for either concatenated or channelized OC-48/STM-16 or Quad OC12/STM-3 SONET/SDH payloads with onchip clock and data recovery and clock synthesis.
LongBoat NOV4431
In the receive path, all framing, descrambling, alarm detection are performed. Full path overhead bytes analyzing and pointer interpretation are implemented on each channel. A serial interface provides insertion/extraction of order-wire and section/line DCC bytes. ATM Cell Processing In ATM-cell processing, the LongBoat performs all cell encapsulation, HEC calculation, cell delineation, payload scrambling/descrambling and idle cell insertion/filtering per channel. Data is received/transmitted from/to a higher layer device using a UTOPIA-Level 3 interface. POS Processing In POS mode, the LongBoat performs all HDLC framing, scrambling/de-scrambling, inter-frame fills, FIFO management and stuffing/de-stuffing operations per channel. Data is received/transmitted from/to higher layer devices using a POS-PHY level 3 interface. Line Interface The LongBoat includes on-chip clock and data recovery for single 2.488 Gbps or Quad 622 Mbps line rates. This clock and data recovery block also implements the Serialize/Deserialize functions. On the receive path, after recovery of the data and its associated clock, data is sent to the SONET/SDH framer via a parallel bus.
SONET/SDH Processing The LongBoat when used in single OC-48 port mode supports both concatenated and channelized traffic with logical channel combinations of STS-12's STS-3's and STSSONET/SDH payloads. When used in the Quad OC-12 ports mode it supports both concatenated and channelized traffic with logical channel combinations of STS-3's and STSSONET/SDH payloads per each port. In the transmit path, this device generates all section and line overhead bytes, in addition to implementing framing, scrambling and alarm indication functions. Full path overhead bytes generation is implemented per channel. It also maps external payloads received through the TelecomBus I/F and adjusts timing reference between system clock and line clock using pointer processor.
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Higher-Layer Interface The LongBoat supports several interfaces to higher layer devices. The component supports UTOPIA Level-3 interface (for ATM cells or frames) and POS-PHY Leve-3 interface for PPP packets in POS mode and for mixture of channels of ATM cells and PPP packets. Also it supports TelecomBus interface for TDM traffic. The three I/Fs are supported simultaneously.
PRELIMINARY
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PRODUCT BRIEF
Access to all SONET/SDH overhead bytes including channel path overhead bytes via a microprocessor port. UTOPIA Level 3 (with packet support) and POS-PHY Level 3 interface to higher layer devices supporting mixture of up to 48 ATM/PPP channels simultaneously. TelecomBus interface for external payloads. Provides TSI (Time Slot Interchange) for gathering any combination of channels. Optional SONET/SDH frame scrambling/descrambling operation (1+X6+X7). Optional self-synchronous ATM cell/frame HDLC packet scrambler (X43+1). Standard IEEE 1149.1 JTAG port. Complies with SONET/SDH standards (Bellcore GR-253, ITU-G.707 and ANSI T1.105) 1.8 volt, 0.18µ CMOS technology with 3.3 tolerant TTL I/O.
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FEATURES
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Fully integrated clock and data recovery module supporting a single 2.488 Gbps or Quad 622 Mbps data streams. STS-48 or Quad STS-12 data streams either concatenated or channelized processing with mapping functions of ATM cells, ATM frames (FB-ATM), PPP packets and external payloads into SONET/SDH payloads. supports channelized traffic with logical channel combinations of STS-12's STS-3's and STS48 STS1's SONET/SDH payloads when using the single OC-48 port mode. Full processing of SONET/SDH section, line and channel path overhead bytes. DCC overhead interface in Rx and Tx paths. Full mapping of payloads received through the TelecomBus I/F including adjusting timing reference between system clock and line clock using pointer processor. APS port to be used between two companion devices.
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APPLICATIONS
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ATM switches Switches & Routers SONET/SDH Add Drop Multiplexers
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Property of Novanet Semiconductor
PRELIMINARY PRODUCT BRIEF LongBoat BLOCK DIAGRAM
Channels Alarms Serial I/F
PMD
OC-48 Framer (channelized)
Pointer Processor
TSI
Cell/Packet Processor
FIFO
Tx UTOPIA 3 & POS-PHY 3
Port 0
PMD OC-12 Framer (channelized) Pointer Processor TSI Cell/Packet Processor
FIFO
PMD
OC-12 Framer (channelized)
Pooce0sor Pr rt s Port 3
Pointer
TSI
Cell/Packet Processor
FIFO
Telecom Bus
APS Cross-Bus/OW i/f
Sec./Line DCC i/f
Microprocessor Interface
Frame Alarms
JTAG Interface
Figure 1: NOV4431 Functional Blocks
Corporate Heaquarters
4 Hacharoshet Street Tel: +972 9 746 4411 Fax: +972 9 746 4422 Email: info@novanetsemi.com
Property of Novanet Semiconductor
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