Details, datasheet, quote on part number: SM5901
PartSM5901
Category
Description
CompanyNippon_Precision_Circuits America
DatasheetDownload SM5901 datasheet
  

 

Features, Applications
compression and non compression type anti-shock memory controller with built-in 1M DRAM

The is a compression and non compression type anti-shock memory controller with built-in 1M DRAM LSI for compact disc players. The compression level can be set in 4 levels, and external 1M DRAM can be connected to expand the memory to 2M bits. Digital attenuator, soft mute and related functions are also incorporated. It operates from 3.3 V wide supply voltage range.

Features

- 2-channel processing - Serial data input2s complement, 16-bit/MSB first, rear-packed format - System clock input384fs (16.9344 MHz)

- Anti-shock memory controller - ADPCM compression method4-level compression mode selectable

21M DRAM (256K4 bits) Internal and external 1M DRAMs 11M DRAM (256K4 bits) Only internal 1M DRAM - Compression mode selectable - Microcontroller interfaceSerial command write and state read-outData residual quantity detector: 15-bit operation, 16-bit output

4-bit compression mode 2.78 s/Mbit 5-bit compression mode 2.22 s/Mbit 6-bit compression mode 1.85 s/Mbit Full-bit non compression mode 0.70 s/MbitExternal memory can be connected

Full-bit settingSoft attenuator functionSoft mute function
Mute 23 ms max. Direct return after soft mute releaseForced mute

- Extension I/O Microcontroller interface for external control using 5 extension I/O pins +3.3 V wide operating voltage range - Schmitt inputs All input pins (including I/O pins) except CLK (system clock) - Reset signal noise elimination Approximately s or longer (65 system

clock pulses) continuous LOW-level reset - 44-pin QFP package (0.8 mm pin pitch)
Noiseless attenuation-level switching (256- step switching 23 ms max.)

Pin number Pine name NTEST1 NTEST2 CLK VSS1 YSRDATA YLRCK YSCK ZSCK ZLRCK ZSRDATA YFLAG YFCLK YBLKCK NRESET ZSENSE VDD1 I/O Ip/O Ip Function H VDD supply pin Microcontroller interface extension I/O 1 Setting L

Microcontroller interface extension I/O 3 Microcontroller interface extension I/O 4 Ground Test pin Test pin Ground 16.9344 MHz clock input Audio serial input data Audio serial input LR clock Audio serial input bit clock Left channel Audio serial output bit clock Audio serial output data Audio serial output LR clock Left channel Signal processor IC RAM overflow flag Crystal-controlled frame clock Subcode block clock signal System reset pin Microcontroller interface status output VDD supply pin Forced mute pin Mute Microcontroller interface latch clock Microcontroller interface serial data Test pin Microcontroller interface shift clock DRAM CAS control DRAM data input/output 2 DRAM data input/output 3 DRAM data input/output 0 DRAM data input/output 1 DRAM WE control DRAM RAS control Test pin DRAM address 8 DRAM address 7 DRAM address 6 DRAM address 5 DRAM address 4 DRAM address 0 DRAM address 1 DRAM address 2 DRAM address 3

Ip : Input pin with pull-up resistor Ip/O : Input/Output pin (With pull-up resistor when a input mode) And in case that only internal 1M DRAM is used, to 44 pin are high impedance, and to 32 pin are input pull up mode.


 

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SM5901A
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