Details, datasheet, quote on part number: SM5906AF
PartSM5906AF
CategoryMultimedia => Audio => Protection => Electronic Shock Protection
TitleElectronic Shock Protection
DescriptionCD-DA, V-CD, SVC Mode Selectable, VDD=2.7 to 3.6V, Video CD Products
CompanyNippon_Precision_Circuits America
DatasheetDownload SM5906AF datasheet
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Features, Applications

The is a shock-proof memory controller LSI for video CD players. The operating mode can be set to CD-DA mode, V-CD mode, or Super V-CD mode, and external memory can be selected from 2 options 16M). It operates from 3.6 V supply voltage range.

Features

2-channel processing Serial data input 2s complement, 16-bit/MSB first Right-justified format Wide capture function (up 4 speed input rate) Selectable 16/24/32-bit clock System clock input 384fs (16.9344 MHz) Shock-proof memory controller Selectable CD-DA/V-CD/SVC mode 2 external DRAM configurations selectable 16M DRAM 4 bits, refresh cycle = 2048 cycle) 4M DRAM 4 bits) Microcontroller interface Serial command write and status read-out Data residual detector: 11-bit operation, 16-bit output (Bits to 15 bit are fixed LOW.) Forced mute Extension I/O Microcontroller interface for external control using 3 extension I/O pins +3.6 V operating voltage range Schmitt inputs All input pins (including I/O pins) except CLK (system clock) Reset signal noise elimination Approximately s or longer (65 system clock pulses) continuous LOW-level reset - 48-pin QFP package (0.5 mm pin pitch)

VSS2 YMLD YDMUTE ZSENSE NRESET YBLKCK YFLAG ZC2PO ZSRDATA ZSCK ZLRCK VDD2

Pin number Pin name NTEST1 TEST2 CLK YC2PO YSRDATA YLRCK YSCK VSS1 VDD2 ZLRCK ZSCK I/O Iu/O Iu Id Function H VDD supply pin Microcontroller interface extension I/O 1 Microcontroller interface extension I/O 2 Microcontroller interface extension I/O 3 Test pin Test pin 16.9344 MHz clock input Serial input C2PO data Serial input data Serial input LR clock Serial input bit clock Ground VDD supply pin Serial output LR clock Serial output bit clock Left channel Right channel Left channel Right channel Test Setting L

Iu : Input pin with pull-up resistor, Id : Input pin with pull-down resistor Iu/O : Input/Output pin (With pull-up resistor when in input mode)

Pin number Pin name ZSRDATA ZC2PO YFLAG YBLKCK NRESET ZSENSE YDMUTE YMLD VSS2 VDD3 YMDATA YMCLK NRAS NCAS D0 D1 NWE A3 VSS4 I/O Iu/O Function H Serial output data Serial output C2PO data Signal processor IC RAM overflow flag Subcode block clock signal System reset pin Microcontroller interface status output Forced mute pin Microcontroller interface latch clock Ground VDD supply pin Microcontroller interface serial data Microcontroller interface shift clock DRAM RAS control DRAM CAS control DRAM data input/output 2 DRAM data input/output 3 DRAM data input/output 0 DRAM data input/output 1 DRAM WE control DRAM address 10 Ground VDD supply pin DRAM address 9 DRAM address 8 DRAM address 7 DRAM address 6 DRAM address 5 DRAM address 4 DRAM address 0 DRAM address 1 DRAM address 2 DRAM address 3 Ground Mute Reset Setting L


 

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