|Category||Communication => Telephony => Caller ID|
|Description||Multi-frame Pocsag Decoder|
|Datasheet||Download SM8212 datasheet
POCSAG Decoder For Multiframe Pagers - BS2 (RF DC-level adjustment signal) before/during reception selectable adjustment timing - 1-bit and 2-bit burst error auto-correction function to 75% duty factor signal coverage - 8 rate error detection condition settings - 76.8 kHz system clock (crystal oscillator) or 38.4 kHz clock output pin - Built-in oscillator capacitor and feedback resistor 3.5 V operating supply voltage - Molybdenum-gate CMOS process realizes low power dissipation - 16-pin SSOP
The is a POCSAG-standard (Post Office Code Standardization Advisory Group) signal processor LSI, which conforms to CCIR recommendation 584 concerning standard international wireless calling codes. The SM8212B supports call messages in either tone, numerical or character outputs at signal speeds or 2400 bps. The signal input stage features a built-in filter. Each of the addresses (max. 8) can be assigned to any frame, which also makes the device configurable for many additional services. Each address can be independently set ON/OFF. Furthermore, built-in buffer memory means decoded information can be fetched in sync with the microcontroller clock, thereby reducing the microcontroller CPU time required. Intermittent-duty method (battery saving (BS) method) control signals, compatible with PLL operation, and Molybdenum-gate CMOS structure makes possible the construction of low-voltage operation, low power dissipation systems. The SM8212B is available in 16-pin SSOPs.FEATURES
- Conforms to POCSAG standard for pagers or 2400 bps signal speed - Multiframe compatible (each address individually controllable) - 8 addresses × 4 sub-address (total of 32 addresses) control - Built-in buffer memory - Supports tone, numeric or character call messages - Built-in input signal filter, with filter ON/OFF and 4 selectable filter characteristics - PLL-compatible battery saving method BS2, BS3 outputs) - BS1 (RF control main output signal) 61-step setup time setting - BS3 (PLL setup signal) 61-step setup time settingTiming Control Buffer Register Flag Register (Ring) Buffer Register
Preamble Pattern Sync Code Idle Code XVSS XT
Pin number Pin name BS2 BS3 SIGNAL XVSS XT XTN VSS CLKO RSTN AREA SCK SDO SDI ATTN VDD i/o Description RF control main output signal RF DC-level adjustment signal PLL setup signal NRZ signal input pin Crystal oscillator ground. Capacitor connected between XVSS and VDD Oscillator input pin Oscillator output pin Ground or 38.4 kHz clock output Hardware clear (reset) Sync code detection output (HIGH for minimum 1 sec. on detection) CPU-to-decoder data transfer sync clock Status and received data output to CPU Data input from CPU (including ID data) Interrupt detect signal output pin (Ready for data transmission when LOW) Supply voltage i = Input, o = Output
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