Details, datasheet, quote on part number: nAD10100K-18
CategoryData Conversion => ADC (Analog to Digital Converters) => 10-14 bit => 12 bit
DescriptionAnalog to Digital Converter ip
CompanyNordic VLSI
DatasheetDownload nAD10100K-18 datasheet


Features, Applications


1.8V power supply SNR typ 58dB for (fin = 10kHz) Low power @ 1.8V and 100kSPS) Compact area (<0.2mm2) Sampling frequency from to 100kHz Programmable resolution. 8, 10 and 12 bits 9 multiplexed single ended inputs Low input capacitance Three power saving idle modes


The is a compact, high-speed, low power to 12 bit monolithic analog-to-digital converter, implemented a 0.18m single poly CMOS process with MiM capacitor option. The converter includes a sample and hold. Using internal references, the full scale range is 1.2V with an input signal range to 1.2V. The full scale range can be set between 0.75V and 1.5V using external references. It operates from a single 1.8V supply. The bias current level for the ADC can be programmed in 8 steps. Hence, the power dissipation of the device can be minimised for the current operation frequency. The nAD10100K-18 has an algorithmic architecture - resulting in low silicon area. The core occupies less than 0.2mm2 of die area in a standard single poly 0.18m CMOS process with MiM capacitor option. The fully differential architecture makes it insensitive to substrate noise. Thus it is ideal as a mixed signal ASIC macro cell.

Supply voltage Power dissipation (100 kSPS) Differential nonlinearity Integral nonlinearity Signal to noise ratio Spurious free dynamic range

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 2.0 Page of 9 November 28th, 2002

(At = 25C, VDD = 1.8V, Sampling Rate = 100kHz, Input frequency 10kHz, 50% duty cycle clock and 300nF Reference decoupling unless otherwise noted)

DC Accuracy Differential Nonlinearity fIN = 0.9991 kHz Integral Nonlinearity fIN = 0.9991 kHz Midscale offset Common Mode Rejection Ratio Gain Error Dynamic Performance Signal to Noise Ratio (without harmonics) fIN = 10 kHz Signal to Noise and Distortion Ratio fIN = 10 MHz Spurious Free Dynamic Range fIN = 10 kHz Analog Input Voltage Range Input Capacitance Reference Voltages Internal reference voltage drift Full scale range (internal reference) Full scale range (external reference) Reference voltage input (external ref) Switching Performance Maximum Conversion Rate Minimum Conversion Rate Pipeline delay Aperture delay, IP Setup time CSTARTN Hold time CSTARTN Output hold time, 0.8 pF load) Output delay time, 0.8 pF load) Aperture delay, with bonding pad

Logic "0" voltage Logic "1" voltage Logic "0" current (VI=VSS) Logic "1" current (VI=VDD) Input Capacitance VDD

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 2.0 Page of 9 November 28th, 2002

Digital Outputs Logic "0" voltage = 2 mA) Logic "1" voltage = 2 mA) Power Supply voltage Supply current (except digital output) Supply voltage Power dissipation (except digital output) (active 100 kSPS) Power dissipation (except digital output) (active 10 kSPS) Power dissipation (except digital output) Power Down Mode Power dissipation (except digital output) Sleep Mode Power dissipation (except digital output) Standby Mode Start-up time from Power down Start-up time from Sleep mode Start-up time from Stand By Junction operating temperature

Test Level I: 100% production tested at +25C Test Level II: 100% production tested at +25C and sample tested at specified temperatures Test Level III: Sample tested only Test Level IV: Parameter is guaranteed by design and characterization testing Test Level V: Parameter is typical value only Test Level VI: 100% production tested at +25C. Guaranteed by design and characterization testing for industrial temperature range

Supply voltages VDD...............................- to +2.2V OVDD..............................- to 3.6V Temperatures Operating to +125C Storage Temperature.. to +125C

Analog In.............- 0.2V to VDD + 0.2V Digital In.........................- to 3.6V REFP....................- 0.2V to VDD + 0.2V REFN....................- 0.2V to VDD + 0.2V CLOCK..........................- to 3.6V Note: Stress above one or more of the limiting values may cause permanent damage to the device.

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 2.0 Page of 9 November 28th, 2002


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