Details, datasheet, quote on part number: nAD10105-18
PartnAD10105-18
CategoryData Conversion => ADC (Analog to Digital Converters) => 10-14 bit => 10 bit
DescriptionAnalog to Digital Converter ip
CompanyNordic VLSI
DatasheetDownload nAD10105-18 datasheet
  

 

Features, Applications

FEATURES

1.8V power supply SNR typ 59dB for (fin = 10MHz) Low power @ 1.8V and 105MSPS) Frequency dependent biasing Internal Sample/Hold Differential input Low input capacitance Power Down and Sleep Mode

APPLICATIONS

Imaging Test equipment Computer scanners Wireless communication Powerline communication Set top boxes Video products

The is a compact, high-speed, low power 10-bit monolithic analog-todigital converter, implemented a 0.18µm single poly CMOS process with MiM capacitor option. The converter includes a high bandwidth sample and hold. Using internal references, the full scale range is ±0.75V. The full scale range can be set between ±0.5V and ±0.75V using external references. It operates from a single 1.8V supply. Its low distortion and high dynamic range offers the performance needed for demanding imaging, multimedia, telecommunications and instrumentation applications. The bias current level for the ADC is automatically adjusted based on the clock input frequency. Hence, the power dissipation of the device is continuously minimised for the current operation frequency.

Supply voltage Supply current (105 MSPS) Power dissipation (10 MSPS) Power dissipation (1050 MSPS) Differential nonlinearity Integral nonlinearity Conversion rate Resolution

Except digital output drivers Except digital output drivers fIN=0.9991MHz

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page of 11 September 10th 2001

The nAD10105-18 has a pipelined architecture - resulting in low input capacitance. Digital error correction of the 9 most significant bits ensures good linearity for input frequencies approaching Nyquist. The nAD10105-18 is compact. The core occupies less than 0.9mm2 of die area in a standard single poly 0.18µm CMOS process. The fully differential architecture makes it insensitive to substrate noise. Thus it is ideal as a mixed signal ASIC macro cell.

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page of 11 September 10th 2001

(At = 25°C, VDD = 1.8V, Sampling Rate = 105MHz, Input frequency = 10MHz, Differential input signal, 50% duty cycle clock unless otherwise noted )

DC Accuracy Differential Nonlinearity fIN = 0.9991 MHz Integral Nonlinearity fIN = 0.9991 MHz Midscale offset Common Mode Rejection Ratio Gain Error Dynamic Performance Signal to Noise Ratio (without harmonics) fIN = 10 MHz fIN = 40 MHz Signal to Noise and Distortion Ratio fIN = 10 MHz Spurious Free Dynamic Range fIN = 10 MHz fIN = 40 MHz Analog Input Voltage Range (differential) Common mode input voltage Input Capacitance (from each input to ground) Reference Voltages Internal reference voltage on pin 10 Internal reference voltage on pin 11 Internal reference voltage drift Negative Input Voltage Positive Input Voltage Reference input voltage range 1) Common mode output voltage Switching Performance Conversion Rate Pipeline Delay Aperture delay, IP Output hold time, IP Output delay time, IP Aperture delay, with bonding pad Output hold time, with bonding pad Output delay time, with bonding pad

VREFNI VREFPI VREFNO VREFPO VREFP-VREFN VCM FS tAP th td tAP th td VIL VIH IIL IIH CIND

Logic "0" voltage Logic "1" voltage Logic "0" current (VI=VSS) Logic "1" current (VI=VDD) Input Capacitance

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page of 11 September 10th 2001


 

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