Details, datasheet, quote on part number: nAD10120-13
PartnAD10120-13
CategoryData Conversion => ADC (Analog to Digital Converters) => 10-14 bit => 10 bit
DescriptionAnalog to Digital Converter ip
CompanyNordic VLSI
DatasheetDownload nAD10120-13 datasheet
  

 

Features, Applications

FEATURES

10-bit ADC to 120 MSPS Conversion Rate Single 1.2 V Power Supply 1.0 V p-p Differential Input Excellent Dynamic Performance 59 dBFS SNR at FIN = 10 MHz 70 dBc SFDR at FIN = 10 MHz 600 MHz Analog Input Bandwidth Low Power Consumption at 120 MSPS at 25 MSPS Dynamic Power Scaling Power Saving Idle Modes Internal Voltage Reference 1.34 mm2 Core Area

TIMING GENERATOR DIGITAL CONTROL DIGITAL CORRECTION

Figure 1. Functional block diagram Communication Receive Channel WLAN / HiperLan / 802.11x Digital Imaging / Video TV / Video / Radio Decoders Graphic Capture demanding applications like broadband communication, digital imaging and multimedia. The ADC consumes only at 120 MSPS operation. Dynamic power scaling means that the power consumption is scaled with the operating frequency resulting in only 20 mW consumption at 25 MSPS operation. Combined with power saving idle modes the ADC is suitable for battery powered devices. The conversion is controlled by the single-ended clock input. Output data is available in a binary offset coded format. Three out-of-range indicator bits are also available for determining if the input signal is over-range, under-range or out-of-range. Implemented in a generic 0.13 m CMOS process, operating from a single 1.2 V supply and employing a fully differential architecture it represents an ideal ADC for highly integrated mixed-signal systems.

APPLICATIONS

The is a monolithic, high-speed, low power, analog-to-digital converter silicon IP. It uses a fully differential multistage pipeline architecture with digital error correction to provide 10-bit accuracy from to 120 MSPS conversion speed. The core includes a wide-band sample-andhold and an internal voltage reference that provides a nominal full-scale range 1.0 V peak-to-peak. The IP is designed for high dynamic performance at input frequencies up to Nyquist and beyond. It thus represents an ideal solution for

Supply Voltage Power Dissipation, @ FCLK = 110 MHz Differential Non Linearity Integral Non Linearity Signal-to-Noise Ration, FIN = 10 MHz Spurious-Free-Dynamic Range, FIN = 10 MHz Hard Macro / TSMC Generic, 8 Metal 0.13 m CMOS mm2 mm

Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway

PRELIMINARY PRODUCT SPECIFICATION 10-bit 120 MSPS Analog-to-Digital Converter IP ELECTRICAL SPECIFICATIONS DC SPECIFICATIONS

= 25 C, VAVDD = VVDD 1.2 V, FCLK = 120 MHz, FIN = 10 MHz, internal references, differential fullscale input signal, 50 % duty cycle clock, and 10nF reference decoupling unless otherwise noted )

DC ACCURACY Resolution No Missing Codes Guaranteed Monotonicity Guaranteed Integral Non Linearity Differential Non Linearity Gain Error Offset Error ANALOG INPUT Input Differential Voltage Range Input Common Mode Voltage Input Impedance Analog Input Bandwidth REFERENCE VOLTAGES Internal Positive Voltage Reference Internal Negative Voltage Reference Internal Reference Range Internal Differential Full-scale Range Internal Reference Common Mode Voltage Internal Voltage Reference Drift External Reference Range External Differential Full Scale Range External Reference Common Mode Voltage POWER SUPPLY Positive Analog Supply Voltage Positive Digital Supply Voltage Negative Supply Voltage Supply Current, Active Supply Current, Standby Supply Current, Sleep Supply Current, Power down Power Dissipation, Active Power Dissipation, Standby Power Dissipation, Sleep Power Dissipation, Power down OPERATING CONDITIONS Junction Operating Temperature

N NMC MON INL DNL G VOS VFSR VVCM,EXT AIBW VREFP VREFN VRR FSR VVCM VRR,EXT FSREXT VRCM,EXT VAVDD VVDD VSS IDD

PRELIMINARY PRODUCT SPECIFICATION 10-bit 120 MSPS Analog-to-Digital Converter IP

= 25 C, VAVDD = VVDD 1.2 V, FCLK = 120 MHz, FIN = 10 MHz, internal references, differential fullscale input signal, 50 % duty cycle clock, and 10nF reference decoupling unless otherwise noted )

SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Input Clock Duty Cycle Pipeline Delay ( Latency ) Output Data Delay Time Output Data Hold Time Aperture Delay Time Aperture Uncertainty ( Jitter ) Start-up Time from Standby Mode Start-up Time from Sleep Mode Start-up Time from Power Down Mode Out-of-Range Recovery Time SIGNAL-TO-NOISE RATIO 120 MSPS, FIN = 10 MHz 120 MSPS, FIN = 40 MHz 120 MSPS, FIN = 72 MHz SIGNAL-TO-NOISE-AND DISTORTION RATIO 120 MSPS, FIN = 10 MHz 120 MSPS, FIN = 40 MHz 120 MSPS, FIN = 72 MHz SPURIOUS FREE DYNAMIC RANGE 120 MSPS, FIN = 10 MHz 120 MSPS, FIN = 40 MHz 120 MSPS, FIN = 72 MHz EFFECTIVE NUMBER OF BITS 120 MSPS, FIN = 5 MHz 120 MSPS, FIN = 10 MHz 120 MSPS, FIN = 40 MHz 120 MSPS, FIN = 72 MHz

FCLK,MAX FCLK,MIN tpd td th tad tjitter tstandby tsleep tpower down tout-of-range SNR

 

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