Part  nAD121025 
Category  Data Conversion => ADC (Analog to Digital Converters) => 1014 bit => 12 bit 
Description  Analog to Digital Converter ip 
Company  Nordic VLSI 
Datasheet  Download nAD121025 datasheet

Features, Applications 
FEATURES 2.5V power supply SNR typ 67dB for (fin = 10MHz) Low power (30mW@2.5V) Sample rate:10MSPS Frequency dependent biasing Internal/sample hold Differential input Low input capacitance APPLICATIONSImaging Test equipment Computer scanners Communications Set top boxes Video products The is a compact, highspeed, low power 12bit monolithic analogtodigital converter, implemented in the TSMC MixedSignal MiM CMOS process. It has 12bit resolution with more than 10 effective bits, and close to 11 bit dynamic range for video frequency signals. The converter includes a high bandwidth sample and hold. The full scale range is ±1V. The full scale range can be set between ±0.5V and ±1V. It operates from a single 2.5V supply. Its low distortion and high dynamic range offers the performance needed for demanding imaging, multimedia, telecommunications and instrumentation applications. The bias current level for the ADC is automatically adjusted based on the clock input frequency. Hence, the power dissipation of the device is continuously minimised for the current operation frequency. supply voltage supply current (10 MSPS) power dissipation (10 MSPS) power dissipation (sleep mode) differential nonlinearity integral nonlinearity conversion rate resolution Except digital output drivers Except digital output drivers fIN=0.9991MHz 10Main office: Nordic VLSI ASA  Vestre Rosten 81, N7075 Tiller, Norway  Phone +4772898900  Fax +4772898989 Revision: 1.0 Page of 11 September 4th, 2001 The nAD121025 has a pipelined architecture  resulting in low input capacitance. Digital error correction of the 11 most significant bits ensures good linearity for input frequencies approaching Nyquist. The nAD121025 is compact. The core occupies less than 1,5mm2 of die area in TSMC Mixed Signal MiM 0.25µm CMOS process. The fully differential architecture makes it insensitive to substrate noise. Thus it is ideal as a mixed signal ASIC macro cell. Main office: Nordic VLSI ASA  Vestre Rosten 81, N7075 Tiller, Norway  Phone +4772898900  Fax +4772898989 Revision: 1.0 Page of 11 September 4th, 2001 (At = 25°C, VDD = 2.5V, Sampling Rate = 10MHz, Input frequency = 10MHz dBFS, Differential input signal, 50% duty cycle clock unless otherwise noted). DC Accuracy Differential Nonlinearity fIN = 0.9991 MHz INL Integral Nonlinearity fIN = 0.9991 MHz VOS Midscale offset CMRR Common Mode Rejection Ratio (of VOS) Dynamic Performance SINAD Signal to Noise and Distortion Ratio fIN = 10 MHz fIN = 40 MHz SNR Signal to Noise Ratio (without harmonics) fIN = 10 MHz SFDR Spurious Free Dynamic Range fIN = 10 MHz fIN = 40 MHz PSRR Power Supply Rejection Ratio (of VOS) Analog Input VFSR Input Voltage Range (differential) VCMI Common mode input voltage CINA Input Capacitance (differential) Reference Voltages VREFN Negative Input Voltage VREFP Positive Input Voltage 1 VRR Reference input voltage range VCM Common mode output voltage Digital Inputs VIL Logic "0" voltage VIH Logic "1" voltage IIL Logic "0" current (VI=VSS) IIH Logic "1" current (VI=VDD) CIND Input Capacitance Digital Outputs VOL Logic "0" voltage = 2 mA) VOH Logic "1" voltage = 2 mA) tH Output hold time tD Output delay time (table continued on next page) DNL Main office: Nordic VLSI ASA  Vestre Rosten 81, N7075 Tiller, Norway  Phone +4772898900  Fax +4772898989 Revision: 1.0 Page of 11 September 4th, 2001 
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