Details, datasheet, quote on part number: nAD1220-18T
PartnAD1220-18T
CategoryData Conversion => ADC (Analog to Digital Converters) => 10-14 bit => 12 bit
DescriptionAnalog to Digital Converter ip
CompanyNordic VLSI
DatasheetDownload nAD1220-18T datasheet
  

 

Features, Applications

FEATURES

3.3V power supply SINAD min 63.2dB for fin = 50MHz Low power @ 3.3V and 20MSPS) Frequency dependent biasing Internal, wideband Track/Hold Differential input Low input capacitance Power Down and Sleep Mode

APPLICATIONS

Imaging Test equipment Computer scanners Wireless communication Powerline communication Set top boxes Video products

The is a compact, high-speed, low power 12-bit monolithic analog-todigital converter, implemented a 0.18µm single poly CMOS process with MiM capacitors and thick oxide transistor option. It has 12-bit resolution with 11 effective bits at low input frequencies, and close to 12 bit dynamic range for video frequency signals. The converter includes a high bandwidth track and hold. Using internal references, the full scale range is ±1V. The full scale range can be set between ±0.75V and ±1.0V using external references. It operates from a single 3.3V supply, while I/O is biased with 1.8V. Its low distortion and high dynamic range offers the performance needed for demanding imaging, multimedia, telecommunications and instrumentation applications. The bias current level for the ADC is automatically adjusted based on the clock input frequency. Hence, the power dissipation of the device is continuously minimised for the current operation frequency.

Supply voltage Supply current (30 MSPS) Power dissipation (15 MSPS) Power dissipation (20 MSPS) Differential nonlinearity Integral nonlinearity Conversion rate Resolution

Except digital output drivers Except digital output drivers fIN=0.9991MHz

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.3 Page of 11 September , 2001

The nAD1220-18T has a pipelined architecture - resulting in low input capacitance. Digital error correction of the 11 most significant bits ensures good linearity for input frequencies approaching Nyquist. The nAD1220-18T is compact. The core occupies less than 4mm2 of die area in the TSMC MiM 0.18µm CMOS process with thick oxide option. The fully differential architecture makes it insensitive to substrate noise. Thus it is ideal as a mixed signal ASIC macro cell.

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.3 Page of 11 September , 2001

(At = 25°C, VDD = 3.3V, Sampling Rate = 20MHz, Input frequency = 15MHz, Differential input signal, 50% duty cycle clock unless otherwise noted )

DC Accuracy Differential Nonlinearity fIN = 0.9991 MHz Integral Nonlinearity fIN = 0.9991 MHz Midscale offset Common Mode Rejection Ratio Gain Error Dynamic Performance Signal to Noise Ratio (without harmonics) fIN = 10 MHz fIN = 50 MHz Signal to Noise and Distortion Ratio fIN = 10 MHz fIN = 50 MHz Spurious Free Dynamic Range fIN = 10 MHz fIN = 50 MHz Analog Input Voltage Range (differential) Common mode input voltage Input Capacitance (from each input to ground) Reference Voltages Internal reference voltage drift Negative Input Voltage Positive Input Voltage Reference input voltage range 1) Common mode output voltage Switching Performance Conversion Rate Pipeline Delay Aperture delay, IP Output hold time, IP Output delay time, IP Aperture delay, with bonding pad Output hold time, with bonding pad Output delay time, with bonding pad

Logic "0" voltage Logic "1" voltage Logic "0" current (VI=VSS) Logic "1" current (VI=VDD) Input Capacitance µA pF

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.3 Page of 11 September , 2001


 

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