Details, datasheet, quote on part number: nAD1230-25
CategoryData Conversion => ADC (Analog to Digital Converters) => 10-14 bit => 12 bit
DescriptionAnalog to Digital Converter ip
CompanyNordic VLSI
DatasheetDownload nAD1230-25 datasheet


Features, Applications


2.5V power supply SNR typ 67dB for (fin = 10MHz) Low power (80mW@2.5V) Sample rate: 30MSPS Frequency dependent biasing Internal/sample hold Differential input Low input capacitance

Imaging Test equipment Computer scanners Communications Set top boxes Video products

The is a compact, high-speed, low power 12-bit monolithic analog-todigital converter, implemented in the TSMC Mixed-Signal MiM CMOS process. It has 12-bit resolution with more than 10 effective bits, and close to 11 bit dynamic range for video frequency signals. The converter includes a high bandwidth sample and hold. The full scale range is 1V. The full scale range can be set between 0.5V and 1V. It operates from a single 2.5V supply. Its low distortion and high dynamic range offers the performance needed for demanding imaging, multimedia, telecommunications and instrumentation applications. The bias current level for the ADC is automatically adjusted based on the clock input frequency. Hence, the power dissipation of the device is continuously minimised for the current operation frequency.

supply voltage supply current (30 MSPS) power dissipation (30 MSPS) power dissipation (10 MSPS) power dissipation (sleep mode) differential nonlinearity integral nonlinearity conversion rate resolution

Except digital output drivers Except digital output drivers Except digital output drivers fIN=0.9991MHz 10

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 Page of 11 September 4th, 2001

The nAD1230-25 has a pipelined architecture - resulting in low input capacitance. Digital error correction of the 11 most significant bits ensures good linearity for input frequencies approaching Nyquist. The nAD1230-25 is compact. The core occupies less than 1,5mm2 of die area in TSMC Mixed Signal MiM 0.25m CMOS process. The fully differential architecture makes it insensitive to substrate noise. Thus it is ideal as a mixed signal ASIC macro cell.

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 Page of 11 September 4th, 2001

(At = 25C, VDD = 2.5V, Sampling Rate = 30MHz, Input frequency = 10MHz dBFS, Differential input signal, 50% duty cycle clock unless otherwise noted).

Midscale offset Common Mode Rejection Ratio (of VOS) Dynamic Performance SINAD Signal to Noise and Distortion Ratio fIN = 10 MHz fIN = 40 MHz SNR Signal to Noise Ratio (without harmonics) fIN = 10 MHz SFDR Spurious Free Dynamic Range fIN = 10 MHz fIN = 40 MHz PSRR Power Supply Rejection Ratio (of VOS) Analog Input VFSR Input Voltage Range (differential) VCMI Common mode input voltage CINA Input Capacitance (differential) Reference Voltages VREFN Negative Input Voltage VREFP Positive Input Voltage 1 VRR Reference input voltage range VCM Common mode output voltage Digital Inputs VIL Logic "0" voltage VIH Logic "1" voltage IIL Logic "0" current (VI=VSS) IIH Logic "1" current (VI=VDD) CIND Input Capacitance Digital Outputs VOL Logic "0" voltage = 2 mA) VOH Logic "1" voltage = 2 mA) tH Output hold time tD Output delay time (table continued on next page)

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 Page of 11 September 4th, 2001


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