Details, datasheet, quote on part number: nAD1240-18TS
CategoryData Conversion => ADC (Analog to Digital Converters) => 10-14 bit => 12 bit
DescriptionAnalog to Digital Converter ip
CompanyNordic VLSI
DatasheetDownload nAD1240-18TS datasheet


Features, Applications


3.3V power supply 150µV input referred noise Low power @ 3.3V and 40MSPS) Compact area (2.47mm2) Frequency dependent biasing Single ended input 1X-2X gain input stage Low input capacitance Two power saving idle modes TSMC Imaging process: 4 metal layers

The is a compact, high-speed, low power 12-bit monolithic analogto-digital converter, implemented in the TSMC imaging 0.18µm CMOS process with MiM capacitor and thick oxide options, and 4 metal layers. The converter includes a single ended to differential low-noise input stage, with or 2X gain, making it ideal for imaging applications. Using internal references, the full scale range in 2X mode and in 1X mode. The full scale range can be reduced by using external references. It operates from a single 3.3V supply. The bias current level for the ADC is automatically adjusted based on the clock input frequency. Hence, the power dissipation of the device is continuously minimised for the current operation frequency. The nAD1240-18TS has a pipelined architecture - resulting in low input capacitance. Digital error correction of the 11 most significant bits ensures good linearity for input frequencies approaching Nyquist. The nAD1240-18TS is compact. The core occupies less than 2.5mm2 of die. The differential architecture makes it insensitive to substrate noise. Thus it is ideal as a mixed signal ASIC macro cell.

Supply voltage Power dissipation Differential nonlinearity Integral nonlinearity Input referred noise Input referred noise

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 Page of 7 May 7th 2002

ELECTRICAL SPECIFICATIONS (At = 25°C, VDD = 3.3V, Sampling Rate = 40MHz, Input frequency = 10MHz, Differential input signal, 50% duty cycle clock and 300nF Reference decoupling unless otherwise noted)

DNL INL VOS G Vnrms VFSR CINA DC Accuracy Differential Nonlinearity fIN = 0.9991 MHz Differential Nonlinearity fIN = 0.9991 MHz Midscale offset Gain Error Dynamic Performance Input referred noise (1X-mode) Input referred noise (2X mode) Analog Input Voltage Range (1X-mode) Input Voltage Range (2X-mode) Input Capacitance (1X-mode) Input Capacitance (1X-mode) Input signal attenuation Reference Voltages Internal reference voltage on ref[0] Internal reference voltage on ref[1] Internal reference voltage drift Negative Input Voltage (external ref) Positive Input Voltage (external ref) Reference input voltage range Switching Performance Maximum Conversion Rate Minimum Conversion Rate Pipeline Delay Aperture delay, IP Output hold time, IP (max 0.2 pF load) Output delay time, IP (max 0.2 pF load)

Logic "0" voltage Logic "1" voltage Logic "0" current (VI=VSS) Logic "1" current (VI=VDD) Input Capacitance Digital Outputs Logic "0" voltage = 2 mA) Logic "1" voltage = 2 mA) Power Supply voltage Supply current (except digital output) Supply voltage Power dissipation active 15 MSPS Power dissipation active 40 MSPS Power dissipation Power Down Mode Power dissipation Standby Mode Start-up time from Power down Start-up time from Stand By Junction operating temperature ±10 0.1

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 Page of 7 May 7th 2002


Overflow-flag Clock Disabling internal references Powerdown control Bias current control Digital power Reference voltages Common ground Analog ground Negative input Input signal

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 Page of 7 May 7th 2002


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