Details, datasheet, quote on part number: NAD1280-18
PartNAD1280-18
CategoryData Conversion => ADC (Analog to Digital Converters) => 10-14 bit => 12 bit
DescriptionAnalog to Digital Converter ip
CompanyNordic VLSI
DatasheetDownload NAD1280-18 datasheet
  

 

Features, Applications

FEATURES

1.8V power supply SNR typ 65dB for (fin = 10MHz) Low power @ 1.8V and 80MSPS) Compact area (0.86mm2) Frequency dependent biasing Differential input Low input capacitance Three power saving idle modes

APPLICATIONS

Imaging Wireless communication WLAN/IEEE 802.11x DVB receivers Powerline communication Video products

The is a compact, high-speed, low power 12-bit monolithic analog-todigital converter, implemented in the TSMC logic 0.18m CMOS process. No mixed mode process options are needed. The converter includes a high bandwidth sample and hold. Using internal references, the full scale range is 0.75V. The full scale range can be set between 0.5V and 0.75V using external references. It operates from a single 1.8V supply. Its low distortion and high dynamic range offers the performance needed for demanding imaging, multimedia, telecommunications and instrumentation applications. The bias current level for the ADC is automatically adjusted based on the clock input frequency. Hence, the power dissipation of the device is continuously minimised for the current operation frequency. The nAD1280-18 has a pipelined architecture - resulting in low input capacitance. Digital error correction of the 11 most significant bits ensures good linearity for input frequencies approaching Nyquist. The nAD1280-18 is compact. The core occupies 0.86mm2 of die area. The fully differential architecture makes it insensitive to substrate noise. Thus it is ideal as a mixed mode in a SoC design.

Supply voltage Power dissipation (80 MSPS) Differential nonlinearity Integral nonlinearity Signal to noise ratio Spurious free dynamic range

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 2.0 Page of 10 December 13th 2002

(At = 25C, VDD = 1.8V, Sampling Rate = 80MHz, Input frequency = 10MHz, Differential input signal, 50% duty cycle clock and 300nF Reference decoupling unless otherwise noted)

DC Accuracy Differential Nonlinearity fIN = 0.9991 MHz Integral Nonlinearity fIN = 0.9991 MHz Midscale offset Common Mode Rejection Ratio Gain Error Dynamic Performance Signal to Noise Ratio (without harmonics) fIN = 10 MHz fIN = 40 MHz 1) fIN = 72 MHz 1) Signal to Noise and Distortion Ratio fIN = 10 MHz Spurious Free Dynamic Range fIN = 10 MHz fIN = 40 MHz fIN = 72 MHz Analog Input Voltage Range (differential) Analog input common mode voltage Input Capacitance (from each input to ground) Input signal attenuation @ 70MHz Reference Voltages Internal reference voltage on pin 10 Internal reference voltage on pin 11 Internal reference voltage drift Negative Input Voltage (external ref) Positive Input Voltage (external ref) Reference input voltage range 2) Common mode voltage output Switching Performance Maximum Conversion Rate Minimum Conversion Rate Pipeline Delay Aperture delay, IP Output hold time, 0.8 pF load) Output delay time, 0.8 pF load) Aperture delay, with bonding pad Output hold time, with bonding pad Output delay time, with bonding pad

Logic "0" voltage Logic "1" voltage Logic "0" current (VI=VSS) Logic "1" current (VI=VDD) Input Capacitance 0.4 AVDD

(table continued on next page) 1) Requires 1ps clock source jitter, and 1.5ps total on-chip jitter.

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 2.0 Page of 10 December 13th 2002

Digital Outputs Logic "0" voltage = 2 mA) Logic "1" voltage = 2 mA) Power Supply voltage Supply current (except digital output) Supply voltage Power dissipation (except digital output) (active 10 MSPS) Power dissipation (except digital output) (active 80 MSPS) Power dissipation (except digital output) Power Down Mode Power dissipation (except digital output) Sleep Mode Power dissipation (except digital output) Standby Mode Start-up time from Power down Start-up time from Sleep mode Start-up time from Stand By Output driver supply voltage Junction operating temperature

Test Level I: 100% production tested at +25C Test Level II: 100% production tested at +25C and sample tested at specified temperatures Test Level III: Sample tested only Test Level IV: Parameter is guaranteed by design and characterization testing Test Level V: Parameter is typical value only Test Level VI: 100% production tested at +25C. Guaranteed by design and characterization testing for industrial temperature range

Supply voltages VDD............................... to +2.2V OVDD.............................. to 3.6V Temperatures Operating to +125C Storage Temperature.. to +125C

Analog In............ 0.2V to VDD + 0.2V Digital In........................ to 3.6V REFP.................... 0.2V to VDD + 0.2V REFN................... 0.2V to VDD + 0.2V CLOCK.......................... to 3.6V Note: Stress above one or more of the limiting values may cause permanent damage to the device.

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 2.0 Page of 10 December 13th 2002


 

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