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Details, datasheet, quote on part number:NT6861
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Datasheet text preview:
NT6861B
8-Bit Microcontroller for Monitor
Features
Operating Voltage Range: 4.5V to 5.5V CMOS technology for low power consumption Crystal oscillator or ceramic resonator* available 6502 8-bit CMOS CPU core 8MHz operation of frequency 24K bytes of ROM maximum 256 bytes of RAM (which stores EDID for DDC1/2B) One 8-bit pre-loadable base timer 14 channels of 8 bit PWM outputs with 5V open drain 2 channel A/D converters with 6-bit resolution 24 bi-directional I/O port pins and 1 I/P pin Hsync/Vsync signal processor Hardware sync signals polarity & freq. evaluator 2 Built-In I C bus interface Supporting VESA DDC1/2B function Six-interrupt sources - INTV (Vsync INT) - INTE (External INT with rising edge trigger) - INTMR (Timer INT ) - INTA (Slave Address Matched INT) - INTD (Shift Register INT) - INTS (SCL GO-LOW INT) Hardware watch-dog timer function 40 pin DIP & 42 pin SDIP package
General Description
NT6861B is a monitor component µC for auto-sync and digital controlled applications. It contains a 6502 8-bit CPU core, 256 bytes of RAM used as working RAM and stack area, 24K bytes of ROM maximum for programming, 14-channel 8-bit PWM D/A converters, 2-channel A/D converters for key detection saving I/O pins, one 8 bit pre-loadable base timer, internal Hsync and Vsync signals processor providing mode detection, watch-dog timer 2 preventing system from abnormal operation, and an I C bus interface. Users can store EDID data in the 128 bytes of RAM for DDC1/2B, so that users can save the cost of dedicated EEPROM for EDID. Half frequency output function can save external one-shot circuit. All of these designs create savings in component costs. * The frequency deviation of ceramic resonator has +/- 6% maximum.
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V1.1
NT6861B
Pin Configuration
[OE] DAC2 DAC1 DAC0 [VPP] RESET VDD GND OSCO OSCI P15 [CE] P14 [A11] P13/HALFHI [A10] P12/HALFHO [A9] P11/AD1 [A8] P10/AD0 P16/INTE [DB7] P27 [DB6] P26 [DB5] P25 [DB4] P24 [DB3] P23
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VSYNCI/INTV/ [A14] HSYNCI DAC3 [PGM] DAC4 [MODE0] DAC5 [MODE1] DAC6 [MODE2] DAC7 P07/HSYNCO [A7] P06/VSYNCO [A6] P05/DAC13 [A5] P04/DAC12 [A4] P03/DAC11 [A3] P02/DAC10 [A2] P01/DAC9 [A1] P00/DAC8 [A0] P31/SCL [A13] P30/SDA [A12] P20 [DB0] P21 [DB1] P22 [DB2]
[OE] DAC2 DAC1 DAC0 [VPP] RESET VDD NC GND OSCO OSCI P15 [CE] P14 [A11] P13/HALFHI [A10] P12/HALFHO [A9] P11/AD1 [A8] P10/AD0 P16/INTE [DB7] P27 [DB6]P26 [DB5] P25 [DB4] P24 [DB3] P23
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VSYNCI/INTV HSYNCI DAC3 [PGM] DAC4 [MODE0] DAC5 [MODE1] NC DAC6 [MODE2] DAC7 [A14] P07/HSYNCO [A7] P06/VSYNCO [A6] P05/DAC13 [A5] P04/DAC12 [A4] P03/DAC11 [A3] P02/DAC10 [A2] P01/DAC9 [A1] P00/DAC8 [A0] P31/SCL [A13] P30/SDA [A12] P20 [DB0] P21 [DB1] P22 [DB2]
NT6861BU
NT6861B NT6861B NT6861B NT6861B
*[
]: OTP Mode
*[
]: OTP Mode
Block Diagram
VDD GND OSCI OSCO INTE VSYNCI/INTV HSYNCI VSYNCO HSYNCO HALFHI HALFHO H/V Sync Signals Processor Watch Dog Timer CPU core 6502 SRAM + STACK 256 Bytes A/D Converter Interrupt Controller 8 Bit Base Timer I/O Ports PWM DACs Timing Generator Program ROM 4/8/12/16/24K Bytes IIC BUS
SCL SDA
DAC0 - DAC7 DAC8 - DAC13
AD0 - AD1
P00 - P07 P10 - P15 P16 P20 - P27 P30 - P31
2
NT6861B
Pin Descriptions
Pin No. 40 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - 23 42 Pin 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 - 24 DAC2 DAC1 DAC0 RESET VDD GND OSCO OSCI P15 P14 P13/HALFHI P12/HALFHO P11/AD1 P10/AD0 P16/INTE P27 - P20 P13 P12 P11 P10 P16 O O O I P P O I I/O I/O I/O I/O I/O I/O I I/O Open drain 12V, D/A converter output 2 Open drain 12V, D/A converter output 1 Open drain 12V, D/A converter output 0 Schmitt trigger input pin, low active reset* Power Ground Crystal OSC output Crystal OSC input Bi-directional I/O pin Bi- directional I/O pin Bi- directional I/O pin, shared with half hsync input Bi- directional I/O pin, shared with half hsync output Bi- directional I/O pin, shared with A/D converter channel 1 input Bi- directional I/O pin, shared with A/D converter channel 0 input Schmitt trigger input pin with internal pull high, shared with external Rising-edge trigger interrupt Bi- directional I/O pin, push-pull structure with high current drive/sink capability Designation Reset Init. I/O Description
*
This RESET pin must be pulled high by external pulled-up resistor (5K suggestion), or it will stay low voltage to reset system all the time.
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