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Details, datasheet, quote on part number:NT6862-5xxxx
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Datasheet text preview:
NT6862-5xxxx
8-Bit Microcontroller for Monitor
Features
Operating voltage range: 4.5V to 5.5V CMOS technology for low power consumption 6502 8-bit CMOS CPU core 8 MHz operation frequency 32K/24K/16K bytes of ROM 512 bytes of RAM One 8-bit base timer 13 channels of 8-bit PWM outputs with 5V open drain 4 channel A/D converters with 6-bit resolution 25 bi-directional I/O port pins (8 dedicated I/O pins) Hsync/Vsync signals processor for separate & composite signals which includes hardware sync signals polarity detection and frequency counters with 2 sets of Hsync counting intervals n Hsync/Vsync polarity controlled output, 5 selectable free run output signals and self-test patterns, automute function, half freq. I/O function n Add a jitter filter at the front end of Hsync input path, reduce the jitter interference of Hysync input n n n n n n n n n n n n Two built-in DDC1/2B+ I2C bus interfaces support VESA
n Two layers of interrupt management NMI interrupt sources - INTE0 (External INT with selectable edge trigger) - INTMUTE (Auto Mute Activated) IRQ interrupt sources - INTS0/1 (SCL Go-low INT) - INTA0/1 (Slave Address Matched INT) - INTTX0/1 (Shift Register INT) - INTRX0/1 (Shift Register INT) - INTNAK0/1 (No Acknowledge) - INTSTOP0/1 (Stop Condition Occurred INT) - INTE1 (External INT with Selectable Edge Trigger) - INTV (VSYNC INT) - INTMR (Base Timer INT) - INTADC (AD Conversion Done INT) n Hardware Watch-dog timer function n 40-pin P-DIP and 42-pin S-DIP packages
General Description
The NT6862 is a new generation monitor µC for auto-sync and digital control applications. Particularly, this chip supports various and efficient functions to allow users to easily develop USB monitors. It contains the 6502 8-bit CPU core, 512 bytes of RAM used as working RAM and stack area, 32K bytes of OTP ROM, 13-channels of 8-bit PWM D/A converters, 4-channel A/D converters for key detection which save I/O pins, one 8-bit pre-loadable base timer, internal Hsync and Vsync signals processor, a Watch-dog timer which prevents the system from abnormal operation, and two I2C bus interfaces. The user can store EDID data in the 128 bytes of RAM for DDC1/2B, so that user can reduce a dedicated EEPROM for EDID. A Half frequency output function can save external one-shot circuit. These designs are committed to reduce component cost. The 42 pin S-DIP IC provides two additional I/O pins port40 & port41, Part number NT6862U represents the SDIP IC. For future reference, port40 & port42 are only available for the 42 pin S-DIP IC.
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V2.2
NT6862-5xxxx
Pin Configurations
40-Pin P-DIP
[PGM] DAC2 DAC1/ADC3 [OE] DAC0/ADC2 [VPP] RESET VDD GND OSCO OSCI P15/INTE0 [CE] P14/PATTERN [A11] P13/HALFI [A10] P12/HALFO [A9] P11/ADC1 [A8] P10/ADC0 P16/INTE1 [DB7] P27 [DB6] P26 [DB5] P25 [DB4] P24 [DB3] P23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSYNCI/INTV [A14] HSYNCI DAC3 [MODE0] DAC4/SCL1 [MODE1] DAC5/SDA1 [MODE2] DAC6 [RESET] CREG P07/HSYNCO [A7] P06/VSYNCO [A6] P05/DAC12 [A5] P04/DAC11 [A4] P03/DAC10 [A3] P02/DAC9 [A2] P01/DAC8 [A1] P00/DAC7 [A0] P31/SCL0 [A13] P30/SDA0 [A12] P20 [DB0] P21 [DB1] P22 [DB2] [PGM] DAC2 DAC1/ADC3 [OE] DAC0/ADC2 [VPP] RESET VDD P40 GND OSCO OSCI P15/INTE0 [CE] P14/PATTERN [A11] P13/HALFI [A10] P12/HALFO [A9] P11/ADC1 [A8] P10/ADC0 P16/INTE1 [DB7] P27 [DB6] P26 [DB5] P25 [DB4] P24 [DB3] P23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSYNCI/INTV [A14] HSYNCI DAC3 [MODE0] DAC4/SCL1 [MODE1] DAC5/SDA1 [MODE2] P41 DAC6 [RESET] CREG P07/HSYNCO [A7] P06/VSYNCO [A6] P05/DAC12 [A5] P04/DAC11 [A4] P03/DAC10 [A3] P02/DAC9 [A2] P01/DAC8 [A1] P00/DAC7 [A0] P31/SCL0 [A13] P30/SDA0 [A12] P20 [DB0] P21 [DB1] P22 [DB2]
NT6862U
NT6862
*[ *[ ]: OTP Mode
]: OTP Mode
42-Pin S-DIP
Block Diagram
VDD CREG GND OSCI OSCO INTE0/1 VSYNCI/INTV HSYNCI VSYNCO HSYNCO PATTERN HALFI HALFO
Voltage Regulator
OTP Program ROM 32K Bytes
IIC BUS
SCL0 SDA0 SCL1 SDA1
T i m i n g Generator SRAM + STACK 512 Bytes CPU core 6502 8 - B i t Base Timer PWM DACs
DAC0 - DAC7 DAC8 - DAC12 ADC0 - ADC3
A/D Converter P00 - P07 P10 - P16 W a t c h Dog Timer I/O Ports P20 - P27 P30 - P31 P40 - P41
Interrupt Controller
H / V Sync Signals Processor
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NT6862-5xxxx
Pin Description
Pin No. 40 Pin 1 42 Pin 1 Designation DAC2 [ PGM ] 2 3 2 3 DAC1/ADC3 DAC0/ADC2 [ OE ] 4 4 RESET [ VPP ] 5 6 7 8 9 5 7 8 9 10 VDD GND OSCO OSCI P15/INTE0 I [P] P P O I I/O DAC1 DAC0 Reset Init. I/O O [I] O O Description Open drain 5V, D/A converter output 2 [OTP ROM program control] Open drain 5V, D/A converter output 1, shared with A/D converter channel 3 input Open drain 5V, D/A converter output 0, shared with A/D converter channel 2 input [OTP ROM program output enable] Schmitt Trigger input pin, low active reset with internal pulled down 50K register * [OTP ROM program supply voltage] Power Ground Crystal OSC output Crystal OSC input Bi-directional I/O pin with internally pulled up 22K register, shared with input pin of external interrupt source0 (NMI), with Schmitt Trigger, selectable triggered, and internally pulled up 22K register Bi-directional I/O pin with internally pulled up 22K register, shared with the output of self test pattern [ OTP ROM program address buffer & chip enable ] Bi-directional I/O pin with internally pulled up 22K register, shared with half Hsync input. [ OTP ROM program address buffer ] Bi-directional I/O pin with internally pulled up 22K register, shared with half Hsync output [ OTP ROM program address buffer ] Bi-directional I/O pin with internally pulled up 22K register, shared with A/D converter channel 1 input [ OTP ROM program address buffer ] Bi-directional I/O pin with internally pulled up 22K register, shared with A/D converter channel 0 input [ OTP ROM program address buffer ] Bi-directional I/O pin with internally pulled up 22K register, shared with input pin of external interrupt source1, with Schmitt Trigger, selectable triggered, and an internal pulled up 22K register
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11
P14/PATTERN [ A15/CE ]
I/O [I] P13 I/O [I] P12 I/O [I] P11 I/O [I] P10 I/O [I] P16 I/O
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12
P13/HALFI [ A11 ]
12
13
P12/HALFO [ A10 ]
13
14
P11/ADC1 [ A9 ]
14
15
P10/ADC0 [ A8 ]
15
16
P16/INTE1
3
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