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Details, datasheet, quote on part number:NT68F62
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Datasheet text preview:
NT68F62
8-Bit Microcontroller for Monitor (32K Flash MTP Type)
Features
Operating voltage range: 4.5V to 5.5V CMOS technology for low power consumption 6502 8-bit CMOS CPU core 8 MHz operation frequency 32K bytes of flash memory for Multi -Times Program 512 bytes of RAM 2Kbytes Masked BootROM for ISP. One 8-bit base timer 13 channels of 8-bit PWM outputs with 5V open drain 4 channel A/D converters with 6-bit resolution 25 bi-directional I/O port pins (8 dedicated I/O pins) Hsync/Vsync signals processor for separate & composite signals, including hardware sync signals polarity detection and freq. counters with 2 sets of Hsync counting intervals Hsync/Vsync polarity controlled output, 5 selectable free run output signals and self-test patterns, automute function, half freq. I/O function Two built-in IIC bus interfaces support VESA DDC1/2B+ Two layers of interrupt management NMI interrupt sources - INTE0 (External INT with selectable edge trigger) - INTMUTE (Auto Mute Activated) IRQ interrupt sources - INTS0/1 (SCL Go-low INT) - INTA0/1 (Slave Address Matched INT) - INTTX0/1 (Shift Register INT) - INTRX0/1 (Shift Register INT) - INTNAK0/1 (No Acknowledge) - INTSTOP0/1 (Stop Condition Occurred INT) - INTE1 (External INT with Selectable Edge Trigger) - INTV (VSYNC INT) - INTMR (Base Timer INT) - INTADC (AD Conversion Done INT) Hardware watch-dog timer function 40-pin P-DIP and 42-pin S-DIP packages
General Description
The NT68F62 is a new generation of monitor µC for autosync and digital control applications. Particularly, this chip supports various functions to allow users to easily develop USB monitors. It contains the 6502 8-bit CPU core, 512 bytes of RAM for use as working RAM and as stack area, 32K bytes of Flash memory, 13-channels of 8-bit PWM D/A converters, 4-channel A/D converters for detection of keys which can save I/O pins, one 8-bit pre-loadable base timer, an internal Hsync and Vsync signals processor and a watch-dog timer, which prevents the system from abnormal operation and two IIC bus interfaces. The user can store EDID data in the 128 bytes of RAM for DDC1/2B, so that the user can reduce a dedicated EEPROM for EDID. The half frequency output function can save the external oneshot circuit. All of these designs are borne of our committment to offer our user savings on component costs. The 42 pin S-DIP IC provides two additional I/O pins port40 & port41, Part number NT68F62U represents the SDIP IC. For future reference, port40 & port42 are only available for the 42 pin S-DIP IC.
1
V1.0
NT68F62
Pin Configurations
40-Pin P-DIP
[PG] DAC2 [0] DAC1/ADC3 [YE] DAC0/ADC2 [VPP] RESET VDD GND [8MHZ]OSCO [0]OSCI [OE/SE] P15/INTE0 [XE] P14/PATTERN [XA5] P13/HALFI [XA4] P12/HALFO [XA3] P11/ADC1 [XA2] P10/ADC0 [1]P16/INTE1 [DB7] P27 [DB6] P26 [DB5] P25 [DB4] P24 [DB3] P23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSYNCI/INTV [XA8] HSYNCI[0] DAC3 [NV] DAC4/SCL1 [ERASE] DAC5/SDA1 [MASS] DAC6 [EXRSTB] CREG[TMR] P07/HSYNCO [XA1] P06/VSYNCO [XA0] P05/DAC12 [XY5] P04/DAC11 [XY4] P03/DAC10 [XY3] P02/DAC9 [XY2] P01/DAC8 [XY1] P00/DAC7 [XY0] P31/SCL0 [XA7] P30/SDA0 [XA6] P20 [DB0] P21 [DB1] P22 [DB2] [PG] DAC2 [0] DAC1/ADC3 [YE] DAC0/ADC2 [VPP] RESET VDD P40 GND [8MHZ]OSCO [0]OSCI [OE/SE] P15/INTE0 [XE] P14/PATTERN [XA5] P13/HALFI [XA4] P12/HALFO [XA3] P11/ADC1 [XA2] P10/ADC0 [1]P16/INTE1 [DB7] P27 [DB6] P26 [DB5] P25 [DB4] P24 [DB3] P23
42-Pin S-DIP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSYNCI/INTV [XA8] HSYNCI[0] DAC3 [NV] DAC4/SCL1 [ERASE] DAC5/SDA1 [MASS] P41 DAC6 [EXRSTB] CREG[TMR] P07/HSYNCO [XA1] P06/VSYNCO [XA0] P05/DAC12 [XY5] P04/DAC11 [XY4] P03/DAC10 [XY3] P02/DAC9 [XY2] P01/DAC8 [XY1] P00/DAC7 [XY0] P31/SCL0 [XA7] P30/SDA0 [XA6] P20 [DB0] P21 [DB1] P22 [DB2]
NT68F62U
NT68F62
*[
]: Flash Mode
*[
]: Flash Mode
Block Diagram
VDD CREG GND OSCI OSCO INTE0/1 VSYNCI/INTV HSYNCI VSYNCO HSYNCO PATTERN HALFI HALFO H/V Sync Signals Processor JEDEC Control Block ISP Control Block Interrupt Controller Watch Dog Timer I/O Ports CPU core 6502 8-Bit Base Timer A/D Converter P00 - P07 P10 - P16 P20 - P27 P30 - P31 P40 - P41 Timing Generator SRAM + STACK 512 Bytes PWM DACs
Voltage Regulator
SCL0 32KB Flash memory & 2KB BootROM IIC BUS SDA0 SCL1 SDA1 DAC0 - DAC7 DAC8 - DAC12 ADC0 - ADC3
2
NT68F62
Pin Description
Pin No. 40 Pin 1 2 42 Pin 1 2 Designation DAC2 DAC1/ADC3 DAC1 Reset Init. I/O O O Description Open drain 5V, D/A converter output 2 Open drain 5V, D/A converter output 1, shared with the A/D converter channel 3 input Open drain 5V, D/A converter output 0, shared with the A/D converter channel 2 input Schmitt Trigger input pin, low active reset with internal pulled down 50K resistor * Power Ground Crystal OSC output Crystal OSC input Bi-directional I/O pin with internal pulled up 22K resistor, shared with input pin of external interrupt source0 (NMI), withSchmitt trigger, selectable triggered, and internal pulled up 22K resistor Bi-directional I/O pin with internal pulled up 22K resistor, shared with the output of the self test pattern Bi-directional I/O pin with internal pulled up 22K resistor, shared with the half hsync input Bi-directional I/O pin with internal pulled up 22K resistor, shared with the half hsync output Bi-directional I/O pin with internal pulled up 22K resistor, shared with the A/D converter channel 1 input Bi-directional I/O pin with internal pulled up 22K resistor, shared with the A/D converter channel 0 input Bi-directional I/O pin with internal pulled up 22K resistor, shared with input pin of external interrupt source1, with Schmitt Trigger, selectable triggered, and an internal pulled up 22K resistor
3
3
DAC0/ADC2
DAC0
O
4 5 6 7 8
4 5 7 8 9
RESET VDD GND OSCO OSCI
I P P O I
9
10
P15/INTE0
I/O
10
11
P14/PATTERN
I/O
11
12
P13/HALFI
P13
I/O
12
13
P12/HALFO
P12
I/O
13
14
P11/ADC1
P11
I/O
14
15
P10/ADC0
P10
I/O
15
16
P16/INTE1
P16
I/O
3
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