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Part: MSM6779B
Category:
Optoelectronics
-> Drivers/Controllers
-> LCDs
-> LCD Segment Drivers->B&W Dot Matrix
Description: 160-DOT Segment Driver (TCP)
Company: Oki Semiconductor
Datasheet: Download MSM6779B datasheet File size : 439 kB
Request For quote: Find where to buy MSM6779B
Datasheet text preview:
PEDL6779B-01
PEDL6779B-01 This version: MSM6779B Sep. 2000
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¡ Semiconductor MSM6779B
¡ Semiconductor 160-DOT SEGMENT DRIVER (TCP)
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GENERAL DESCRIPTION
The MSM6779B is a LCD dot matrix segment driver. Fabricated in CMOS technology, the device consists of 160-bit latches I and II, a 160-bit level shifter, and a 4-level driver. The MSM6779B latches the 4-bit parallel display data sent from a microcontroller or a LCD controller to generate a LCD driving signal. This MSM6779B has a power-save function that sets all the drivers except one to the low supply current status (IDD SBY). This driver's 3V-operation allows significant reduction in current consumption, suitable for battery-driving. The bias voltage to specify a drive level can be supplied externally. The MSM6779B can be used for various types of LCD panels.
FEATURES
· Logic supply voltage : 2.7 V to 5.5 V · LCD drive voltage : A wide range from 14 V to 28 V · Applicable LCD duty : 1/64 to 1/256 · The bias voltage can be supplied externally. · LCD outputs : 160 · A power-save function to reduce power consumption in a large-screen LCD panel. · A 4-bit parallel data transfer to reduces its transfer speed to 1/4 of conventional serial transfer, providing low power consumption. · Data transfer clock frequency : 6.5 MHz · 35mm-wide-film TCP Tin-plating User area : 8 mm
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PEDL6779B-01 ¡ Semiconductor MSM6779B
BLOCK DIAGRAM
O1 O2 O3 O158 O159 O160
V1L V3L V4L VEEL
V1R 160-DOT 4-LEVEL DRIVER V4R VEER VDD VEE
´
3R
V
DF DISPOFF
160-bit LEVEL SHIFTER
DD
VSS LOAD 160-bit LATCH (II)
V´
D0 D1 D2 D3
DATA CONTROL
160-bit LATCH (I) (4X40)
SHL
20-bit SHIFT REGISTER
CP EIO1
CONTROL CIRCUIT
EIO2
VDD VSS
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PEDL6779B-01 ¡ Semiconductor MSM6779B
PIN CONFIGURATION (TOP VIEW)
O160 O159 O158 V1R V3R V4R VEER VDDR SHL VSS EIO2 D0 D1 D2 D3 CP LOAD DF DISPOFF EIO1 VDDL VEEL V4L V3L V1L
O3 O2 O1
Note: The drawing shown does not specify the exact outline of the TCP; it only specifies the pin layout.
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