Details, datasheet, quote on part number: ZSDRAM
PartZSDRAM
CategoryASICs => Mega Macrocells
TitleMega Macrocells
DescriptionSynchronous Embedded DRAM
CompanyOki Semiconductor
DatasheetDownload ZSDRAM datasheet
  

 

Features, Applications

Embedded Synchronous DRAM Mega Macrocell 0.25m Mixed 2.5-V/3-V MG63P/64P/65P CSA

CONTENTS Description................................................................................................................................................................1 Features.....................................................................................................................................................................1 Signal Descriptions.................................................................................................................................................4 Functional Description............................................................................................................................................ 5 Power On Sequence...........................................................................................................................................5 Bank Activate Command.................................................................................................................................5 Read and Write Access Modes........................................................................................................................5 Precharge Command.........................................................................................................................................8 Auto Refresh Command (CBR Refresh).........................................................................................................9 Data Mask...........................................................................................................................................................9 No Operation (NOP) Command...................................................................................................................11 Address and DQM vs. Bit Width..................................................................................................................11 DQM Control Bits............................................................................................................................................11 Timing Diagrams.................................................................................................................................................... 13 Command Truth Table..................................................................................................................................23 Current State Truth Table..............................................................................................................................23 AC Characteristics (Vdd to 85C)...............................................................................25 Design Guidlines.................................................................................................................................................... 26 DRAM Test Pad Location...............................................................................................................................31 SDRAM Macrocell Pin Information (Ex. x 256 Bits 16 Banks).....................................................32

The Embedded Synchronous Dynamic Random Access Memory (SDRAM) Mega Macrocell is a featured element in OKI's 0.25m Customer Structured Array (CSA) family. These Mega Macrocells use 3-layer, 4-layer, and 5-layer metal. There are two types of reconfigurable 100-MHz SDRAM cores. The configurations are to 8 Mbits in 512-kbits increments and 128 bits wide in type I, and to 16 Mbits in 1-Mbit increments and 256 bits wide in type II.

FEATURES

Fully synchronous to positive clock edge to 100-MHz clock frequency Read Latency: 2 Random column access every clock Non-multiplexed address Separated Input and Output Byte data control by DQM Single power supply 0.2 V Auto (CBR) refresh, 512 refresh cycles 8 ms


 

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