Details, datasheet, quote on part number: 2N5064RLRA
CategoryDiscrete => Thyristors => SCR (Silicon Controlled Rectifiers)
DescriptionSilicon Controlled Rectifier .8A 25V , Package: TO-92 (TO-226), Pins=3
CompanyON Semiconductor
DatasheetDownload 2N5064RLRA datasheet
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Features, Applications
2N5060 Series Sensitive Gate Silicon Controlled Rectifiers

Annular PNPN devices designed for high volume consumer applications such as relay and lamp drivers, small motor controls, gate drivers for larger thyristors, and sensing and detection circuits. Supplied in an inexpensive plastic TO-226AA (TO-92) package which is readily adaptable for use in automatic insertion equipment. Sensitive Gate Trigger Current 200 µA Maximum Low Reverse and Forward Blocking Current 50 µA Maximum, = 110°C Low Holding Current 5 mA Maximum Passivated Surface for Reliability and Uniformity Device Marking: Device Type, e.g., 2N5060, Date Code

Rating Peak Repetitive Off­State Voltage(1) (TJ to 110°C, Sine Wave, to 60 Hz, Gate Open) 2N5062 2N5064 Symbol VDRM, VRRM IT(RMS) IT(AV) 0.51 0.255 ITSM 10 Amps 0.8 Amp TO­92 (TO­226AA) CASE 029 STYLE 1 2 Value Unit Volts

On-State Current RMS (180° Conduction Angles; = 80°C) *Average On-State Current (180° Conduction Angles) (TC = 67°C) (TC = 102°C) *Peak Non-repetitive Surge Current, 25°C (1/2 cycle, Sine Wave, 60 Hz) Circuit Fusing Considerations = 8.3 ms) *Forward Peak Gate Power (Pulse Width 1.0 µsec; = 25°C)

1 I2t PGM PG(AV) IGM VRGM TJ Tstg +150 A2s Watt 2 3 Cathode Gate Anode

*Forward Average Gate Power (TA = 8.3 ms) *Forward Peak Gate Current (Pulse Width 1.0 µsec; = 25°C) *Reverse Peak Gate Voltage (Pulse Width 1.0 µsec; = 25°C) *Operating Junction Temperature Range *Storage Temperature Range *Indicates JEDEC Registered Data.

Preferred devices are recommended choices for future use and best overall value. See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet.

(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded.

Characteristic *Thermal Resistance, Junction to Case(1) Thermal Resistance, Junction to Ambient *Lead Solder Temperature (Lead Length 1/16 from case, 10 s Max) Symbol RJC RJA Max 200 +230* Unit °C/W °C

*Peak Repetitive Forward or Reverse Blocking Current(2) (VAK = Rated VDRM or VRRM) = 110°C IDRM, IRRM 50 µA

*Peak Forward On­State Voltage(3) (ITM 1.2 A peak = 25°C) Gate Trigger Current (Continuous dc)(4) *(VAK = 7 Vdc, = 100 Ohms) Gate Trigger Voltage (Continuous dc)(4) *(VAK = 7 Vdc, = 100 Ohms) *Gate Non­Trigger Voltage (VAK = Rated VDRM, = 100 Ohms) Holding Current (4) *(VAK = 7 Vdc, initiating current = 20 mA) Turn-On Time Delay Time Rise Time (IGT = 1 mA, VD = Rated VDRM, Forward Current 1 A, di/dt = 6 A/µs Turn-Off Time (Forward Current 1 A pulse, Pulse Width = 50 µs, 0.1% Duty Cycle, di/dt = 6 A/µs, dv/dt = 20 V/µs, IGT = 1 mA) = ­40°C VTM IGT VGT VGD td tr Volts 1.7 Volts µA

Critical Rate of Rise of Off­State Voltage (Rated VDRM, Exponential) *Indicates JEDEC Registered Data. (1) This measurement is made with the case mounted "flat side down" on a heat sink and held in position by means of a metal clamp over the curved surface. (2) RGK 1000 is included in measurement. (3) Forward current applied for 1 ms maximum duration, duty cycle 1%. (4) RGK current is not included in measurement. dv/dt 30 V/µs

Peak Repetitive Off State Forward Voltage Peak Forward Blocking Current Peak Repetitive Off State Reverse Voltage Peak Reverse Blocking Current Peak on State Voltage Holding Current Reverse Blocking Region (off state) Reverse Avalanche Region Anode ­

+ Voltage IDRM at VDRM Forward Blocking Region (off state)


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