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Part: 2N7002LT3
Category:
Discrete
-> Transistors
-> FETs (Field Effect Transistors)
-> MOSFETs
Description: Small Signal MOSFET 115 MA, 60 Volts , Package: SOT-23 (TO-236), Pins=3
Company: ON Semiconductor
Datasheet: Download 2N7002LT3 datasheet File size : 62 kB
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Datasheet text preview:
2N7002LT1
Preferred Device
Small Signal MOSFET 115 mAmps, 60 Volts
NChannel SOT23
MAXIMUM RATINGS
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) Drain Current Continuous TC = 25°C (Note 1.) Continuous TC = 100°C (Note 1.) Pulsed (Note 2.) GateSource Voltage Continuous Nonrepetitive (tp 50 µs) Symbol VDSS VDGR ID ID IDM Value 60 60 ±115 ±75 ±800 Unit Vdc Vdc mAdc
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115 mAMPS 60 VOLTS RDS(on) = 7.5 W
NChannel 3
VGS VGSM
±20 ±40
Vdc Vpk 1
THERMAL CHARACTERISTICS
Characteristic Total Device Dissipation FR5 Board (Note 3.) TA = 25°C Derate above 25°C Thermal Resistance, Junction to Ambient Total Device Dissipation Alumina Substrate,(Note 4.) TA = 25°C Derate above 25°C Thermal Resistance, Junction to Ambient Junction and Storage Temperature Symbol PD Max 225 1.8 556 300 2.4 RJA TJ, Tstg 417 55 to +150 °C/W °C Unit mW mW/°C °C/W mW mW/°C
2
3
RJA PD
1 2
SOT23 CASE 318 STYLE 21
1. The Power Dissipation of the package may result in a lower continuous drain current. 2. Pulse Test: Pulse Width 300 µs, Duty Cycle 2.0%. 3. FR5 = 1.0 x 0.75 x 0.062 in. 4. Alumina = 0.4 x 0.3 x 0.025 in 99.5% alumina.
MARKING DIAGRAM & PIN ASSIGNMENT
Drain
3
702 W
1 2
Gate 702 W
Source = Device Code = Work Week
ORDERING INFORMATION
Device 2N7002LT1 2N7002LT3 Package SOT23 SOT23 Shipping 3000 Tape & Reel 10,000 Tape & Reel
Preferred devices are recommended choices for future use and best overall value.
© Semiconductor Components Industries, LLC, 2000
1
December, 2000 Rev. 4
Publication Order Number: 2N7002LT1/D
2N7002LT1
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
DrainSource Breakdown Voltage (VGS = 0, ID = 10 µAdc) Zero Gate Voltage Drain Current (VGS = 0, VDS = 60 Vdc) GateBody Leakage Current, Forward (VGS = 20 Vdc) GateBody Leakage Current, Reverse (VGS = 20 Vdc) TJ = 25°C TJ = 125°C V(BR)DSS IDSS IGSSF IGSSR 60 1.0 500 100 100 Vdc µAdc nAdc nAdc
ON CHARACTERISTICS (Note 2.)
Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) OnState Drain Current (VDS 2.0 VDS(on), VGS = 10 Vdc) Static DrainSource OnState Voltage (VGS = 10 Vdc, ID = 500 mAdc) (VGS = 5.0 Vdc, ID = 50 mAdc) Static DrainSource OnState Resistance (VGS = 10 V, ID = 500 mAdc) TC = 25°C TC = 125°C (VGS = 5.0 Vdc, ID = 50 mAdc) TC = 25°C TC = 125°C Forward Transconductance (VDS 2.0 VDS(on), ID = 200 mAdc) VGS(th) ID(on) VDS(on) rDS(on) gFS 80 7.5 13.5 7.5 13.5 mmhos 3.75 0.375 Ohms 1.0 500 2.5 Vdc mA Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Output Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Reverse Transfer Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Ciss Coss Cr s s 50 25 5.0 pF pF pF
SWITCHING CHARACTERISTICS (Note 2.)
TurnOn Delay Time TurnOff Delay Time (VDD = 25 Vdc, ID ^ 500 mAdc, RG = 25 , RL = 50 , Vgen = 10 V) td(on) td(off) 20 40 ns ns
BODYDRAIN DIODE RATINGS
Diode Forward OnVoltage (IS = 11.5 mAdc, VGS = 0 V) Source Current Continuous (Body Diode) Source Current Pulsed 2. Pulse Test: Pulse Width 300 µs, Duty Cycle 2.0%. VSD IS ISM 1.5 115 800 Vdc mAdc mAdc
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2
2N7002LT1
TYPICAL ELECTRICAL CHARACTERISTICS
2.0 1.8 I D, DRAIN CURRENT (AMPS) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VDS, DRAIN SOURCE VOLTAGE (VOLTS) TA = 25°C I D, DRAIN CURRENT (AMPS) VGS = 10 V 9V 8V 7V 6V 5V 4V 3V 9.0 10 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VGS, GATE SOURCE VOLTAGE (VOLTS) 9.0 10 0.8 0.6 0.4 0.2 1.0 VDS = 10 V -55°C 125°C 25°C
Figure 1. Ohmic Region
Figure 2. Transfer Characteristics
r DS(on) , STATIC DRAIN-SOURCE ON-RESISTANCE (NORMALIZED)
2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 -60 -20 +20 +60 T, TEMPERATURE (°C) +100 +140 VGS = 10 V ID = 200 mA
VGS(th) , THRESHOLD VOLTAGE (NORMALIZED)
2.4
1.2 1.05 1.1 1.10 1.0 0.95 0.9 0.85 0.8 0.75 0.7 -60 -20 +20 +60 T, TEMPERATURE (°C) +100 +140 VDS = VGS ID = 1.0 mA
Figure 3. Temperature versus Static DrainSource OnResistance
Figure 4. Temperature versus Gate Threshold Voltage
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3
2N7002LT1 INFORMATION FOR USING THE SOT23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.037 0.95
interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.037 0.95
0.079 2.0 0.035 0.9 0.031 0.8
inches mm
SOT23 POWER DISSIPATION The power dissipation of the SOT23 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from t h e device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT23 package, PD can be calculated as follows:
PD = TJ(max) TA R J A
one can calculate the power dissipation of the device which in this case is 225 milliwatts.
PD = 150°C 25°C 556°C/W = 225 milliwatts
The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C,
The 556°C/W for the SOT23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.
SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. · Always preheat the device. · The delta temperature between the preheat and soldering should be 100°C or less.* · When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. · The soldering temperature and time shall not exceed 260°C for more than 10 seconds. · When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. · After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. · Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.
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2N7002LT1
PACKAGE DIMENSIONS
SOT23 (TO236) CASE 31808 ISSUE AF
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
A L
3 1 2
BS
V
G C D H K J
DIM A B C D G H J K L S V
INCHES MIN MAX 0.1102 0.1197 0.0472 0.0551 0.0350 0.0440 0.0150 0.0200 0.0701 0.0807 0.0005 0.0040 0.0034 0.0070 0.0140 0.0285 0.0350 0.0401 0.0830 0.1039 0.0177 0.0236
MILLIMETERS MIN MAX 2.80 3.04 1.20 1.40 0.89 1.11 0.37 0.50 1.78 2.04 0.013 0.100 0.085 0.177 0.35 0.69 0.89 1.02 2.10 2.64 0.45 0.60
STYLE 21: PIN 1. GATE 2. SOURCE 3. DRAIN
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