Details, datasheet, quote on part number: CS3842AAN
CompanyON Semiconductor
DatasheetDownload CS3842AAN datasheet


Features, Applications
CS3842AAN/D Single CS3842A Provides Control for 500 W/200 kHz Current-Mode Power Supply

With the introduction of the CS3842A PWM IC, current­mode is possible for power supplies of a wide range of output power levels. It's low cost makes the CS3842A particularly attractive in low power to DC converter applications. But because this IC can provide a high output current (1.0 A peak, 200 mA average), it is also capable of driving large power MOSFETS which can switch high amounts of power. Current­Mode vs. Voltage­Mode Control In a switching power supply, the output voltage is controlled by varying the conduction duty cycle of the power switch(es). Traditionally duty cycle control was done by comparing the amplified difference of the output voltage feedback signal and a fixed stable reference to the sawtooth waveform derived from an oscillator. This constitutes the basic voltage mode control (VMC) scheme. VMC was later improved by allowing a sample of the input voltage to vary the slope of the sawtooth waveform. This feed forward scheme provided excellent line regulation in most of the popular circuit topologies. However, the task of compensating voltage mode converters has not been simple due to its resonant peak and 40 dB/decade roll off associated with the output LC filter.

In current mode control, (CMC) the control signal represents the peak inductor current and forms a second loop in the circuit (Figure 1). The advantages of current mode control are: Instantaneous correction to line voltage variations; the inductor current slope varies with input voltage. Stable power supply designs; the pole associated with the inductor is eliminated. Equal current sharing in paralleled power stages when both share the same control signal and have the same current sense circuits. No current limit amplifier is needed. Flux balancing exists in push­pull circuits. Disadvantages: Slope compensation is required for peak versus average inductor current error and for compensating instabilities associated with load disturbances in single ended topologies operating at greater than 50% duty cycle. Premature shutdown due to the turn on current spike caused by the reverse diode recovery of the output free wheeling diode. Runaway conditions when half bridge topology is operated in current­mode control.

Figure 1. Basic Circuit Using Current­Mode Control
(b) IAVG. is Constant for Varying Duty Cycle, (Constant Load)
Figure 2. Peak Current Detection is Used to Keep IAVG Constant for Varying Duty Cycles

If the current sense signal is properly filtered, noise induced problems including the turn on spike can be avoided. By deliberately adding more slope to the current sense signal, or subtracting it from the control voltage signal, the instability due to greater than 50% duty cycle operation can be overcome. Slope compensation aids in reducing uncertainty at the point of trigger in the PWM comparator when shallow current ramps are involved. It also helps the peak current appear higher than the turn­on spike. This eliminates premature shutdown. Figure 2a illustrates how peak current detection in current mode control produces a change in the average current by relying on the feed forward property of current mode to compensate for line voltage variations. If a slope equal to one­half the negative going inductor current slope is added to the current sense signal, or subtracted from the control signal, this error is corrected (Figure 2b).

Current­Mode Control With the CS3842A Figure 3 shows a CS3842A block diagram containing the basic functions necessary to implement current­mode control. This device will operate from 30 V from a low impedance voltage source or can be current fed if the current is limited to less than 30 mA. The CS3842A is designed to be driven from the rectified line voltage for start­up, requiring a current of only 0.5 mA(typ). An auxiliary supply voltage is needed when the device is used as in Figure 4. When operating with a supply voltage between 10 V and V, a bootstrap circuit provides more than V to overcome the device's under­voltage lockout circuit turn­ON threshold. The wide hysteresis band (6.0 V) accommodates variations in the input voltage.

Internal Bias 2.50 V Output Enable NOR S + VFB ­ Error Amplifier 2R R Current Sensing Comparator PWM Latch VOUT

The Oscillator Section After VREF is stabilized, the timing capacitor, CT charges through RT to about 2.7 V, and then discharges to about 1.1 V for every cycle of the oscillator. Since CT must begin charging from 0 volts instead V on the first cycle, the ON time is longer than in subsequent cycles. To avoid this ON time discrepancy the CS3842A latches the output in its low state until the end of the first cycle (Figure 5). The internal current source which discharges CT is trimmed to provide an accurate maximum duty cycle clamp without relying on external timers to synchronize the oscillator. The timing components can be selected, to set the frequency of the oscillator, and the maximum duty cycle.

Typical waveforms illustrating CS3842A operation are shown in Figure 6. During the discharge time of the OSC waveform, the oscillator internally disables the output to limit the maximum duty cycle. When VIN increases, the slope of the switch current (the combination of the inductor current slope referred to the primary, the transformer magnetizing current, and any slope compensation) increases such to provide instant duty cycle correction without using the error amplifier's dynamic range. If a step increase in load current occurs, the error amplifier shifts the control line to a higher level to allow the inductor to conduct more current. Since the rate of change of the current on the inductor is fixed by the voltage applied, (if the peak current does not intersect the control line) the duty cycle clamp will time out first and prevent the conduction time from exceeding the maximum ON time. Since the output voltage drops due to the load increase, the down­slope of the inductor current decreases, allowing the current pulse to quickly converge to a steady state value.

Figure 5. The First Pulse is Blanked Out Because it Exceeds the Maximum Duty Cycle Clamp


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