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Part: MC100E136FN
Category:
Logic
-> Counters
Description: 5V Ecl 6-Bit Universal Up/down Counter , Package: Plcc, Pins=28
Company: ON Semiconductor
Datasheet: Download MC100E136FN datasheet File size : 65 kB
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Datasheet text preview:
MC10E136, MC100E136 5V ECL 6 Bit Universal Up/Down Counter
T h e MC10E/100E136 is a 6-bit synchronous, presettable, cascadable universal counter. The device generates a look-ahead-carry output and accepts a look-ahead-carry input. These two features allow for the cascading of multiple E136's for wider bit width counters that operate at very nearly the same frequency as the stand alone counter. The CLOUT output will pulse LOW for one clock cycle one count before the E136 reaches terminal count. The COUT output will pulse LOW for one clock cycle when the counter reaches terminal count. For more information on utilizing the look-ahead-carry features of the device please refer to the applications section of this data sheet. The differential COUT output facilitates the E136's use in programmable divider and self-stopping counter applications. Unlike the H136 and other similar universal counter designs the E136 carry out and look-ahead-carry out signals are registered on chip. This design alleviates the glitch problem seen on many counters where the carry out signals are merely gated. Because of this architecture there are some minor functional differences between the E136 and H136 counters. The user, regardless of familiarity with the H136, should read this data sheet carefully. Note specifically (see logic diagram) the operation of the carry out outputs and the look-ahead-carry in input when utilizing the master reset. When left open all of the input pins will be pulled LOW via an input pulldown resistor. The master reset is an asynchronous signal which when asserted will force the Q outputs LOW. The Q outputs need not be terminated for the E136 to function properly, in fact if these outputs will not be used in a system it is recommended to save power and minimize noise that they be left open. This practice will minimize switching noise which can reduce the maximum count frequency of the device or significantly reduce margins against other noise in the system. The 100 Series contains temperature compensation.
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1 28
MC10E136FN AWLYYWW PLCC28 FN SUFFIX CASE 776 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week
1 28
MC100E136FN AWLYYWW
ORDERING INFORMATION
Device MC10E136FN MC10E136FNR2 MC100E136FN MC100E136FNR2 Package PLCC28 PLCC28 PLCC28 PLCC28 Shipping 37 Units/Rail 500 Units/Reel 37 Units/Rail 500 Units/Reel
· · · · · · · · · ·
550 MHz Count Frequency Fully Synchronous Up and Down Counting Look-Ahead-Carry Input and Output Asynchronous Master Reset PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V NECL Mode Operating Range: VCC= 0 V with VEE= 4.2 V to 5.7 V Internal Input Pulldown Resistors ESD Protection: > 2 KV HBM, > 100 V MM Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D · Flammability Rating: UL94 code V0 @ 1/8", Oxygen Index 28 to 34 · Transistor Count = 506 devices
© Semiconductor Components Industries, LLC, 2002
1
April, 2002 Rev. 4
Publication Order Number: MC10E136/D
MC10E136, MC100E136
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
D3 25 D2 S2 S1 VEE CLK CIN CLIN 26 27 28 1 2 3 4 5 6 7 8 9 10 11 D4 24 D5 23 VCCO 22 Q5 21 Q4 20 VCCO 19 18 17 16 Q3 Q2 QM 0
COUT COUT
CLOUT
QM 1
Pinout: 28-lead PLCC (Top View)
15 14 13 12
VCCO COUT COUT CLOUT DQ RQ
QM 0
VCC
PIN NAMES
PIN D0 D5 Q0 Q5 S1, S2 MR CLK COUT, COUT CLOUT CIN CLIN VCC, VCCO VEE FUNCTION ECL Preset Data Inputs ECL Data Outputs Mode Control Pins Master Reset ECL Clock Input DQ RQ
ECL Look-Ahead-Carry Out (Active LOW) DQ RQ ECL Carry-In Input (Active LOW) ECL Look-Ahead-Carry In Input (Active LOW) Positive Supply Negative Supply
FUNCTION TABLE (Expanded truth table on page 5)
S1 L L L H H H X S2 L H H L L H X CIN X L H L H X X MR L L L L L L H CLK Z Z Z Z Z Z X Function Preset Parallel Data Increment (Count Up) Hold Count Decrement (Count Down) Hold Count Hold Count Reset (Qn = LOW)
DQ
CLIN
S1 S2
CIN
S
E136 Universal Up/Down Counter Logic Diagram
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2
MR CLK
D0
Q0 D1
ECL Differential Carry-Out Output (Active LOW)
Q1
D2 - D4
Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Bits 2 - 4
D1 MR D0 VCCO Q0 Q1 VCCO * All VCC and VCCO pins are tied together on the die.
Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay.
DQ SQ
DQ
S
Q2 - Q4 D5
Q5
MC10E136, MC100E136
MAXIMUM RATINGS (Note 1)
Symbol VCC VEE VI Iout TA Tstg JA JC VEE Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage ode u o age NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) PECL Operating Range NECL Operating Range Tsol Wave Solder <2 to 3 sec @ 248°C 1. Maximum Ratings are those values beyond which device damage may occur. 0 LFPM 500 LFPM std bd 28 PLCC 28 PLCC 28 PLCC Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 8 8 6 6 50 100 0 to +85 65 to +150 63.5 43.5 22 to 26 4.2 to 5.7 5.7 to 4.2 265 Units V V V V mA mA °C °C °C/W °C/W °C/W V V °C
10E SERIES PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 1)
0°C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 2) Output LOW Voltage (Note 2) Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current 0.5 0.3 3980 3050 3830 3050 Min Typ 125 4070 3210 3995 3285 Max 150 4160 3370 4160 3520 150 0.5 0.25 4020 3050 3870 3050 Min 25°C Typ 125 4105 3210 4030 3285 Max 150 4190 3370 4190 3520 150 0.3 0.2 4090 3050 3940 3050 Min 85°C Typ 125 4185 3227 4110 3302 Max 150 4280 3405 4280 3555 150 Unit mA mV mV mV mV µA µA
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / 0.06 V. 2. Outputs are terminated through a 50 ohm resistor to VCC2 volts.
10E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= 5.0 V (Note 1)
0°C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 2) Output LOW Voltage (Note 2) Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current 0.5 0.3 1020 1950 1170 1950 Min Typ 125 930 1790 1005 1715 Max 150 840 1630 840 1480 150 0.5 0.065 980 1950 1130 1950 Min 25°C Typ 125 895 1790 970 1715 Max 150 810 1630 810 1480 150 0.3 0.2 910 1950 1060 1950 Min 85°C Typ 125 815 1773 890 1698 Max 150 720 1595 720 1445 150 Unit mA mV mV mV mV µA µA
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / 0.06 V. 2. Outputs are terminated through a 50 ohm resistor to VCC2 volts.
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