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Part: MC100E137FN
Category:
Logic
-> Counters
Description: 5V Ecl 8-Bit Ripple Counter , Package: Plcc, Pins=28
Company: ON Semiconductor
Datasheet: Download MC100E137FN datasheet File size : 65 kB
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Datasheet text preview:
MC10E137, MC100E137 5V ECL 8 Bit Ripple Counter
The MC10E/100E137 is a very high speed binary ripple counter. The two least significant bits were designed with very fast edge rates while the more significant bits maintain standard ECLinPSt output edge rates. This allows the counter to operate at very high frequencies while maintaining a moderate power dissipation level. The device is ideally suited for multiple frequency clock generation as well as a counter in a high performance ATE time measurement board. Both asynchronous and synchronous enables are available to maximize the device's flexibility for various applications. The asynchronous enable input, A_Start, when asserted enables the counter while overriding any synchronous enable signals. The E137 features XORed enable inputs, EN1 and EN2, which are synchronous to the CLK input. When only one synchronous enable is asserted the counter becomes disabled on the next CLK transition; all outputs remain in the previous state poised for the other synchronous enable or A_Start to be asserted to re-enable the counter. Asserting both synchronous enables causes the counter to become enabled on the next transition of the CLK. If EN1 (or EN2) and CLK edges are coincident, sufficient delay has been inserted in the CLK path (to compensate for the XOR gate delay and the internal D-flip flop setup time) to insure that the synchronous enable signal is clocked correctly, hence, the counter is disabled. All input pins left open will be pulled LOW via an input pulldown resistor. Therefore, do not leave the differential CLK inputs open. Doing so causes the current source transistor of the input clock gate to become saturated, thus upsetting the internal bias regulators and jeopardizing the stability of the device. The asynchronous Master Reset resets the counter to an all zero state upon assertion. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation. · Differential Clock Input and Data Output Pins · VBB Output for Single-Ended Use · Synchronous and Asynchronous Enable Pins · Asynchronous Master Reset · PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V · NECL Mode Operating Range: VCC= 0 V with VEE= 4.2 V to 5.7 V · Internal Input Pulldown Resistors · ESD Protection: > 2 KV HBM, > 100 V MM · Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test · Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D · Flammability Rating: UL94 code V0 @ 1/8", Oxygen Index 28 to 34 · Transistor Count = 330 devices
© Semiconductor Components Industries, LLC, 2002
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1 28
MC10E137FN AWLYYWW PLCC28 FN SUFFIX CASE 776 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week
1 28
MC100E137FN AWLYYWW
ORDERING INFORMATION
Device MC10E137FN MC10E137FNR2 MC100E137FN MC100E137FNR2 Package PLCC28 PLCC28 PLCC28 PLCC28 Shipping 37 Units/Rail 500 Units/Reel 37 Units/Rail 500 Units/Reel
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April, 2002 Rev. 4
Publication Order Number: MC10E137/D
MC10E137, MC100E137
PIN DESCRIPTION
PIN CLK, CLK Q0-Q7, Q0-Q7 A_Start EN1, EN2 MR VBB VCC, VCCO VEE FUNCTION ECL Differential Clock Inputs ECL Differential Q Outputs ECL Asynchronous Enable Input ECL Synchronous Enable Inputs Asynchronous Master Reset Reference Voltage Output Positive Supply Negative Supply CLK Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. VBB 3 4 5 6 7 8 Q0 9 Q1 10 Q1 11 VCCO 13 12 Q2 Q2 VEE CLK A_Start EN1 EN2 26 27 28 1 2 25 24 23 22
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Q7 Q7 Q6 Q6 VCCO 21 Q5 20 Q5 19 18 17 16
Q4 Q4 VCC Q3 Q3
Pinout: 28-Lead PLCC (Top View)
15 14
LOGIC DIAGRAM
A_Start EN1 EN2 D CLK CLK CLK CLK VBB MR R Q Q CLK CLK D R Q Q
MR VCCO Q0
* All VCC and VCCO pins are tied together on the die. Q0 Q0 Q1 Q1 Q7 Q7
CLK CLK D R
Q Q
CLK CLK D R
Q Q
SEQUENTIAL TRUTH TABLE
Function Reset Count EN1 X L L L H H H H L L L L L L H H H H H L L L X EN2 X L L L L L L L L L L L H H H H H L L L L L X A_Start X L L L L L H H H L L L L L L L L L L L L L X MR H L L L L L L L L L L L L L L L L L L L L L H CLK X Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z X Q7 L L L L L L L L L L L L L L L L L L L L L L L Q6 L L L L L L L L L L L L L L L L L L L L L L L Q5 L L L L L L L L L L L L L L L L L L L L L L L Q4 L L L L L L L L L L L L L L L L L L L L L L L Q3 L L L L L L L L L L H H H H H H H H H H H H L Q2 L L L L L L H H H H L L L L L L H H H H H H L Q1 L L H H H H L L H H L L L L H H L L L L H H L Q0 L H L H H H L H L H L H H H L H L L L H L H L
Stop Asynch Start
Count
Stop Synch Start
Stop Count
Reset
Z = Low to High Transition
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MC10E137, MC100E137
MAXIMUM RATINGS (Note 1)
Symbol VCC VEE VI Iout IBB TA Tstg JA JC VEE Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode In ut Voltage Input NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) PECL Operating Range NECL Operating Range 0 LFPM 500 LFPM std bd 28 PLCC 28 PLCC 28 PLCC Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 8 8 6 6 50 100 ± 0.5 0 to +85 65 to +150 63.5 43.5 22 to 26 4.2 to 5.7 5.7 to 4.2 265 Units V V V V mA mA mA °C °C °C/W °C/W °C/W V V °C
Tsol Wave Solder <2 to 3 sec @ 248°C 1. Maximum Ratings are those values beyond which device damage may occur.
10E SERIES PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 1)
0°C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 2) Output LOW Voltage (Note 2) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 3) Input HIGH Current Input LOW Current 0.5 0.3 3980 3050 3830 3050 3.62 2.2 Min Typ 121 4070 3210 3995 3285 Max 145 4160 3370 4160 3520 3.73 4.6 150 0.5 0.25 4020 3050 3870 3050 3.65 2.2 Min 25°C Typ 121 4105 3210 4030 3285 Max 145 4190 3370 4190 3520 3.75 4.6 150 0.3 0.2 4090 3050 3940 3050 3.69 2.2 Min 85°C Typ 121 4185 3227 4110 3302 Max 145 4280 3405 4280 3555 3.81 4.6 150 Unit mA mV mV mV mV V V µA µA
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / 0.06 V. 2. Outputs are terminated through a 50 ohm resistor to VCC2 volts. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
10E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= 5.0 V (Note 1)
0°C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 2) Output LOW Voltage (Note 2) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 3) Input HIGH Current Input LOW Current 0.5 0.3 1020 1950 1170 1950 1.38 2.8 Min Typ 121 930 1790 1005 1715 Max 145 840 1630 840 1480 1.27 0.4 150 0.5 0.065 980 1950 1130 1950 1.35 2.8 Min 25°C Typ 121 895 1790 970 1715 Max 145 810 1630 810 1480 1.25 0.4 150 0.3 0.2 910 1950 1060 1950 1.31 2.8 Min 85°C Typ 121 815 1773 890 1698 Max 145 720 1595 720 1445 1.19 0.4 150 Unit mA mV mV mV mV V V µA µA
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / 0.06 V. 2. Outputs are terminated through a 50 ohm resistor to VCC2 volts. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
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