|
|
Part: MC100EP40
Category:
Timing Circuits
-> Clock Generators
Description:
Company: ON Semiconductor
Datasheet: Download MC100EP40 datasheet File size : 65 kB
Request For quote: Find where to buy MC100EP40
Datasheet text preview:
MC100EP40 3.3V / 5V ECL Differential Phase-Frequency Detector
The MC100EP40 is a threestate phasefrequency detector intended for phaselocked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design significantly reduces the dead zone of the detector. For proper operation, the input edge rate of the R and V inputs should be less than 5 ns. The device is designed to work with a 3.3 V / 5 V power supply. When Reference (R) and Feedback (FB) inputs are unequal in frequency and/or phase the differential UP (U) and DOWN (D) outputs will provide pulse streams which when subtracted and integrated provide an error voltage for control of a VCO. When Reference (R) and Feedback (FB) inputs are 80 ps or less in phase difference, the Phase Lock Detect pin will indicate lock by a high state (VOH). The VTX (VTR, VTR, VTFB, VTFB) pins offer an internal termination network for 50 W line impedance environment shown in Figure 2. An external sinking supply of VCC2 V is required on VTX pin(s). If you short the two differential VTR and VTR (or VTFB and VTFB) together, you provide a 100 W termination resistance that is compatible with LVDS signal receiver termination. For more information on termination of logic devices, see AND8020. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. For more information on Phase Lock Loop operation, refer to AND8040. Special considerations are required for differential inputs under No Signal conditions to prevent instability.
http://onsemi.com MARKING DIAGRAM
20 20 1 TSSOP20 DT SUFFIX CASE 948E 100 EP40 ALYW 1
A L Y W
= Assembly Location = Wafer Lot = Year = Work Week
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device MC100EP40DT Package TSSOP20 Shipping 75 Units/Rail
· · · · · · ·
Maximum Frequency > 2 GHz Typical Fully Differential Advanced High Band Output Swing of 400 mV Theoretical Gain = 1.11 Trise 97 ps Typical, Ffall 70 ps Typical The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V · NECL Mode Operating Range: VCC = 0 V with VEE = 3.0 V to 5.5 V · 50 W Internal Termination Resistor
MC100EP40DTR2 TSSOP20 2500 Tape & Reel
© Semiconductor Components Industries, LLC, 2002
1
October, 2002 Rev. 7
Publication Order Number: MC100EP40/D
MC100EP40
VCC PLD 20 19 VCC 18 D 17 D 16 U 15 U 14 VCC 13 NC 12 VEE 11
PIN DESCRIPTION
PIN U, U D, D FB, FB R, R FUNCTION ECL Up Differential Outputs ECL Down Differential Outputs ECL Feedback Differential Inputs ECL Reference Differential Inputs ECL Phase Lock Detect Function ECL Internal Termination for R ECL Internal Termination for R ECL Internal Termination for FB ECL Internal Termination for FB Reference Voltage Output Positive Supply Negative Supply No Connect
1
2
3
4
5 FB
6 R
7 R
8
9
10
PLD VTR VTR VTFB VTFB VBB VCC VEE NC
VEE VTFB VTFB FB
VTR VTR VBB
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. 20Lead Pinout (Top View)
VTR 50 W R R 50 W VTR U A A S Reset FF R C D B VTFB Reset 50 W (V) FB FB 50 W VTFB VBB D B B D R FF S B D Reset D D D Reset U A C C A U U
Figure 2. Logic Diagram ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value N/A N/A > 4 kV > 400 V > 2 kV Level 1 UL 94 V0 @ 0.125 in 699 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
http://onsemi.com
2
MC100EP40
MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI Iout IBB TA Tstg qJ A qJ C Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (JunctiontoAmbient) Thermal Resistance (JunctiontoCase) Wave Solder 0 LFPM 500 LFPM std bd <2 to 3 sec @ 248°C 20 TSSOP 20 TSSOP 20 TSSOP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 6 6 6 50 100 ± 0.5 40 to +85 65 to +150 140 100 23 to 41 265 Units V V V V mA mA mA °C °C °C/W °C/W °C/W °C
2. Maximum Ratings are those values beyond which device damage may occur.
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
40°C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) PLD Input HIGH Voltage (SingleEnded) Input LOW Voltage (SingleEnded) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 5) Input HIGH Current Input LOW Current 150 U, U, B, B Min 100 2225 1775 1355 2075 1355 1775 2.0 1875 Typ 128 2350 1900 1480 Max 160 2475 2025 1605 2420 1675 1975 3.3 150 150 Min 100 2275 1800 1355 2075 1355 1775 2.0 1875 25°C Typ 130 2400 1925 1480 Max 160 2525 2050 1605 2420 1675 1975 3.3 150 150 Min 110 2300 1825 1355 2075 1355 1775 2.0 1875 85°C Typ 140 2425 1950 1480 Max 170 2550 2075 1605 2420 1675 1975 3.3 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to 2.2 V. 4. All loading with 50 W to VCC2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
http://onsemi.com
3
Others parts begin by mc
|
|
|
