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Part: MC100EP446FA
Category:
Logic
-> Converters->Serial/Parallel Converters
Description: 3.3V / 5V Ecl 8-Bit Differential Parallel/serial Converter , Package: Lqfp, Pins=32
Company: ON Semiconductor
Datasheet: Download MC100EP446FA datasheet File size : 65 kB
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MC10EP446, MC100EP446 3.3V/5V 8 Bit CMOS/ECL/TTL Data Input Parallel/Serial Converter
The MC10/100EP446 is an integrated 8bit parallel to serial data converter. The device is designed with unique circuit topology to operate for NRZ data rates up to 3.2 Gb/s. The conversion sequence from parallel data into a serial data stream is from bit D0 to D7. The parallel input pins D0D7 are configurable to be threshold controlled by CMOS, ECL, or TTL level signals. The serial data rate output can be selected at internal clock data rate or twice the internal clock data rate using the CKSEL pin. Control pins are provided to reset (SYNC) and disable internal clock circuitry (CKEN). In either CKSEL modes, the internal flipflops are triggered on the rising edge for CLK and the multiplexers are switched on the falling edge of CLK, therefore, all associated specification limits are referenced to the negative edge of the clock input. Additionally, VBB pin is provided for singleended input condition. The 100 Series devices contain temperature compensation network.
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MCXXX EP446 AWLYYWW LQFP32 FA SUFFIX CASE 873A 32 1 XXX A WL YY WW = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week
· · · · ·
3.2 Gb/s Typical Data Rate Capability Differential Clock and Serial Outputs VBB Output for Single-ended Input Applications Asynchronous Data Reset (SYNC)
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V · NECL Mode Operating Range: VCC = 0 V with VEE = 3.0 V to 5.5 V · Open Input Default State
*For additional information, see Application Note AND8002/D
· Safety Clamp on Inputs · Parallel Interface Can Support PECL, TTL or CMOS
ORDERING INFORMATION
Device MC10EP446FA MC10EP446FAR2 MC100EP446FA MC100EP446FAR2 Package LQFP32 Shipping 250 Units/Tray
LQFP32 2000/Tape & Reel LQFP32 250 Units/Tray
LQFP32 2000/Tape & Reel
İ Semiconductor Components Industries, LLC, 2002
1
May, 2002 Rev. 4
Publication Order Number: MC10EP446/D
MC10EP446, MC100EP446
D0 D1 D2 D3 D4 D5 D6 18 D7 17 16 15 14 VEE PCLK PCLK VCC SOUT SOUT VCC VCC 13 12 11 10 9 1 2 3 4 5 6 7 8 VEE
24 VCC VCF VEF VEE SYNC SYNC VBB2 VCC 25 26 27 28 29 30 31 32
23
22
21
20
19
MC10EP446 MC100EP446
CKEN
CKSEL
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. 32Lead LQFP Pinout (Top View)
PIN DESCRIPTION
PIN D0*D7* SOUT, SOUT CLK*, CLK* PCLK, PCLK SYNC*, SYNC** CKSEL* CKEN*, CKEN* VCF VEF VBB1, VBB2 VCC VEE FUNCTION ECL, CMOS, or TTL Parallel Data Input ECL Differential Serial Data Output ECL Differential Clock Input ECL Differential Parallel Clock Output ECL Conversion Synchronizing Differential Input (Reset)*** ECL Clock Input Selector ECL Clock Enable Differential Input ECL, CMOS, or TTL Input Selector ECL Reference Mode Connection Reference Voltage Output Positive Supply Negative Supply
* Pins will default LOW when left open. ** Pins will default HIGH when left open. *** The rising edge of SYNC will asynchronously reset the internal circuitry. The falling edge of the SYNC followed by the falling edge of CLK initiates the conversion process synchronously on the next rising edge of CLK.
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CKEN
VCC
CLK
CLK
VBB1
MC10EP446, MC100EP446
TRUTH TABLE
FUNCTION PIN CKSEL SOUT: PCLK = 8:1 CLK: SOUT = 1:1 CLK SOUT CKEN SYNC Synchronously Disables Normal Parallel to Serial Conversion Asynchronously Resets Internal FlipFlops* HIGH LOW SOUT: PCLK = 8:1 CLK: SOUT = 1:2 CLK SOUT Synchronously Enables Normal Parallel to Serial Conversion Synchronous Enable
*The rising edge of SYNC will asynchronously reset the internal circuitry. The falling edge of the SYNC followed by the falling edge of CLK initiates the conversion process synchronously on the next rising edge of CLK.
INPUT VOLTAGE LEVEL SELECTION TABLE
INPUT FUNCTION ECL Mode CMOS Mode TTL Mode* CONNECT TO VCF PIN VEF Pin No Connect 1.5 V $ 100 mV
*For TTL Mode, if no external voltage can be provided, the reference voltage can be provided by connecting the appropriate resistor between VCF and VEE pins. Power Supply 3.3 V 5.0 V Resistor Value 10% (Tolerance) 1.5 kW 500 W
DATA INPUT OPERATING VOLTAGE TABLE
POWER SUPPLY (VCC,VEE) PECL NECL DATA INPUTS (D [0:7]) CMOS p N/A TTL p N/A PECL p N/A NECL N/A p
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