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Part: MC100EP451FA
Category:
Logic
-> Registers
Description: 3.3V / 5V Ecl 6-Bit Differential Register With Master Reset , Package: Lqfp, Pins=32
Company: ON Semiconductor
Datasheet: Download MC100EP451FA datasheet File size : 65 kB
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Datasheet text preview:
MC10EP451, MC100EP451 3.3V / 5V ECL 6-Bit Differential Register with Master Reset
The MC10/100EP451 is a 6bit fully differential register with common clock and SingleEnded Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have a 75 kW pulldown resistor internally. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to http://onsemi.com MARKING DIAGRAM*
LQFP32 FA SUFFIX CASE 873A
MCxxx EP451 AWLYYWW 32 1
· · · · ·
450 ps Typical Propagation Delay Maximum Frequency > 3.0 GHz Typical Asynchronous Master Reset 20 ps Skew Within Device, 35 ps Skew DeviceToDevice
xxx A WL YY WW
= 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V With VEE = 0 V · NECL Mode Operating Range: VCC = 0 V With VEE = 3.0 V to 5.5 V · Open Input Default State
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device MC10EP451FA MC10EP451FAR2 MC100EP451FA MC100EP451FAR2 Package LQFP32 Shipping 250 Units/Tray
· Safety Clamp on Inputs
LQFP32 2000 Tape & Reel LQFP32 250 Units/Tray
LQFP32 2000 Tape & Reel
İ Semiconductor Components Industries, LLC, 2002
1
September, 2002 Rev. 5
Publication Order Number: MC10EP451/D
MC10EP451, MC100EP451
D4 D5 D5 Q5 Q5 VEE Q4 Q4 D0 D0 24 D4 D3 D3 VEE MR D2 D2 D1 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 D3 D3 D1 D0 D0 CLK CLK VCC Q0 Q0 D Q Q3 Q3 R 23 22 21 20 19 18 17 16 15 14 VCC Q3 Q3 VCC Q2 Q2 Q1 Q1 R D2 D2 D Q Q2 Q2 D1 D1 D Q Q1 Q1 R R D Q Q0 Q0
MC10EP451 MC100EP451
13 12 11 10 9
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. 32Lead LQFP Pinout (Top View) PIN DESCRIPTION
PIN D [0:5]*, D [0:5]* MR* CLK*, CLK* Q [0:5], Q [0:5] VCC VEE FUNCTION ECL Differential Data Inputs ECL Master Reset Input ECL Differential Clock Inputs ECL Differential Data Outputs Positive Supply Negative Supply CLK CLK
D4 D4
D
Q
Q4 Q4
R D5 D5
D
Q
Q5 Q5
R VEE
MR
* Pins will default LOW when left open.
Figure 2. Logic Diagram ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW N/A > 2 kV > 200 V > 2 kV Level 2 Oxygen Index: 28 to 34 UL 94 V0 @ 0.125 in 919 Devices
Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.
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MC10EP451, MC100EP451
MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI Iout TA Tstg qJ A qJ C Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Wave Solder 0 LFPM 500 LFPM std bd <2 to 3 sec @ 248°C 32 LQFP 32 LQFP 32 LQFP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 6 6 6 50 100 40 to +85 65 to +150 80 55 12 to 17 265 Units V V V V mA mA °C °C °C/W °C/W °C/W °C
2. Maximum Ratings are those values beyond which device damage may occur. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3) 40°C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage (SingleEnded) Input LOW Voltage (SingleEnded) Input HIGH Voltage Common Mode Range (Differential) (Note 5) Input HIGH Current Input LOW Current 0.5 Min 80 2165 1365 2090 1365 2.0 Typ 95 2290 1490 Max 125 2415 1615 2415 1690 3.3 150 0.5 Min 80 2230 1430 2155 1430 2.0 25°C Typ 95 2355 1555 Max 125 2480 1680 2480 1755 3.3 150 0.5 Min 80 2290 1470 2215 1490 2.0 85°C Typ 95 2415 1615 Max 125 2540 1740 2540 1815 3.3 150 Unit mA mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to 2.2 V. 4. All loading with 50 W to VCC2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6) 40°C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 7) Output LOW Voltage (Note 7) Input HIGH Voltage (SingleEnded) Input LOW Voltage (SingleEnded) Input HIGH Voltage Common Mode Range (Differential) (Note 8) Input HIGH Current Input LOW Current 0.5 Min 80 3865 3065 3790 3065 2.0 Typ 95 3990 3190 Max 125 4115 3315 4115 3390 5.0 150 0.5 Min 80 3930 3130 3855 3130 2.0 25°C Typ 95 4055 3255 Max 125 4180 3380 4180 3455 5.0 150 0.5 Min 80 3990 3170 3915 3190 2.0 85°C Typ 95 4115 3315 Max 125 4240 3440 4240 3515 5.0 150 Unit mA mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to 0.5 V. 7. All loading with 50 W to VCC2.0 volts. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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