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Part: MC100EP51DT
Category:
Logic
-> Flip-Flops
Description: 3.3V / 5V Ecl D Flip Flop With Reset And Differential Clock , Package: Soic, Pins=8
Company: ON Semiconductor
Datasheet: Download MC100EP51DT datasheet File size : 65 kB
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Datasheet text preview:
MC10EP51, MC100EP51 3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock
The MC10/100EP51 is a differential clock D flipflop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flipflop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP51 allow the device to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the CLK input will be biased at VCC/2. The 100 Series contains temperature compensation.
http://onsemi.com MARKING DIAGRAMS*
8 1 SO8 D SUFFIX CASE 751 HEP51 ALYW 1 8 1 TSSOP8 DT SUFFIX CASE 948R HP51 ALYW 1 1 1 8 KP51 ALYW 8 KEP51 ALYW
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· 350 ps Typical Propagation Delay · Maximum Frequency > 3 GHz Typical · PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V · NECL Mode Operating Range: VCC = 0 V with VEE = 3.0 V to 5.5 V · Open Input Default State
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H = MC10 K = MC100 A = Assembly Location
L = Wafer Lot Y = Year W = Work Week
· Safety Clamp on Inputs
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device MC10EP51D MC10EP51DR2 MC100EP51D MC100EP51DR2 MC10EP51DT MC10EP51DTR2 MC100EP51DT Package SO8 SO8 SO8 SO8 TSSOP8 TSSOP8 TSSOP8 Shipping 98 Units/Rail 2500 Tape & Reel 98 Units/Rail 2500 Tape & Reel 100 Units/Rail 2500 Tape & Reel 100 Units/Rail 2500 Tape & Reel
MC100EP51DTR2 TSSOP8
© Semiconductor Components Industries, LLC, 2001
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April, 2001 Rev. 3
Publication Order Number: MC10EP51/D
MC10EP51, MC100EP51
PIN DESCRIPTION
RESET 1 8 VCC PIN CLK*, CLK* Reset* R D 2 D Flip-Flop CLK 3 6 Q 7 Q D* Q, Q VCC VEE FUNCTION ECL Clock Inputs ECL Asynchronous Reset ECL Data Input ECL Data Outputs Positive Supply Negative Supply
* Pins will default LOW when left open.
TRUTH TABLE
CLK 4 5 VEE
D L H X
R L L H
CLK Z Z X
Q L H L
Figure 1. 8Lead Pinout (Top View) and Logic Diagram ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection
Z = LOW to HIGH Transition
Value 75 kW N/A Human Body Model Machine Model Charged Device Model > 2 kV > 200 V > 2 kV Level 1 UL94 code V0 A 1/8" 28 to 34 165 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.) Flammability Rating Oxygen Index Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2.)
Symbol VCC VEE VI Iout TA Tstg JA JC JA JC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode In ut Voltage Input NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Wave Solder 0 LFPM 500 LFPM std bd 0 LFPM 500 LFPM std bd <2 to 3 sec @ 248°C 8 SOIC 8 SOIC 8 SOIC 8 TSSOP 8 TSSOP 8 TSSOP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 6 6 6 50 100 40 to +85 65 to +150 190 130 41 to 44 185 140 41 to 44 265 Units V V V V mA mA °C °C °C/W °C/W °C/W °C/W °C/W °C/W °C
2. Maximum Ratings are those values beyond which device damage may occur.
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MC10EP51, MC100EP51
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3.)
40°C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 4.) Output LOW Voltage (Note 4.) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 5.) Input HIGH Current Input LOW Current 0.5 Min 26 2165 1365 2090 1365 2.0 Typ 34 2290 1490 Max 44 2415 1615 2415 1690 3.3 150 0.5 Min 26 2230 1430 2155 1430 2.0 25°C Typ 35 2355 1555 Max 45 2480 1680 2480 1755 3.3 150 0.5 Min 28 2290 1490 2215 1490 2.0 85°C Typ 37 2415 1615 Max 47 2540 1740 2540 1815 3.3 150 Unit mA mV mV mV mV V µA µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to 2.2 V. 4. All loading with 50 ohms to VCC2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6.)
40°C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 7.) Output LOW Voltage (Note 7.) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 8.) Input HIGH Current Input LOW Current 0.5 Min 26 3865 3065 3790 3065 2.0 Typ 34 3990 3190 Max 44 4115 3315 4115 3390 5.0 150 0.5 Min 26 3930 3130 3855 3130 2.0 25°C Typ 35 4055 3255 Max 45 4180 3380 4180 3455 5.0 150 0.5 Min 28 3990 3190 3915 3190 2.0 85°C Typ 37 4115 3315 Max 47 4240 3440 4240 3515 5.0 150 Unit mA mV mV mV mV V µA µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to 0.5 V. 7. All loading with 50 ohms to VCC2.0 volts. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = 5.5 V to 3.0 V (Note 9.)
40°C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 10.) Output LOW Voltage (Note 10.) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 11.) Input HIGH Current Input LOW Current 0.5 Min 26 1135 1935 1210 1935 VEE+2.0 Typ 34 1010 1810 Max 44 885 1685 885 1610 0.0 150 0.5 Min 26 1070 1870 1145 1870 VEE+2.0 25°C Typ 35 945 1745 Max 45 820 1620 820 1545 0.0 150 0.5 Min 28 1010 1810 1085 1810 VEE+2.0 85°C Typ 37 885 1685 Max 47 760 1560 760 1485 0.0 150 Unit mA mV mV mV mV V µA µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 ohms to VCC2.0 volts. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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