The MC14518B dual BCD counter and the MC14520B dual binary counter are constructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. Each consists of two identical, independent, internally synchronous 4stage counters. The counter stages are type D flipflops, with interchangeable Clock and Enable lines for incrementing on either the positivegoing or negativegoing transition as required when cascading multiple stages. Each counter can be cleared by applying a high level on the Reset line. In addition, the MC14518B will count out of all undefined states within two clock periods. These complementary MOS up counters find primary use in multistage synchronous or ripple counting applications requiring low power dissipation and/or high noise immunity.
PDIP16 P SUFFIX CASE 648 MC14518BCP AWLYYWW SOIC16 DW SUFFIX CASE SOEIAJ16 F SUFFIX CASE 966 MC14518B ALYW 1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week 14518B
Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Internally Synchronous for High Internal and External Speeds Logic EdgeClocked Design Incremented on Positive Transition of Clock or Negative Transition on Enable· Capable of Driving Two Lowpower TTL Loads or One Lowpower Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 3.) Operating Temperature Range Storage Temperature Range Lead Temperature (8Second Soldering) Value 0.5 to VDD +150 260 Unit mW °C
Device MC14518BDW MC14518BDWR2 Package SOIC16 SOEIAJ16 Shipping 1000/Tape & Reel See Note 1. See Note 1.
2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: 7.0 mW/_C From To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
Clock Enable Reset Action Increment Counter Increment Counter No Change No Change No Change No Change Q0 thru = 0
4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 5. The formulas given are for the typical characteristics only 6. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL 50) Vfk where: in µA (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and = 0.002.