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Details, datasheet, quote on part number: MC14553B
 
 
Part numberMC14553B
CategoryLogic => Counters => CMOS/BiCMOS->4000 Family
TitleCMOS/BiCMOS->4000 Family
Description3-digit BCD Counter
CompanyON Semiconductor
DatasheetDownload MC14553B datasheet
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Specifications, Features, Applications

The MC14553B 3­digit BCD counter consists of 3 negative edge triggered BCD counters that are cascaded synchronously. A quad latch at the output of each counter permits storage of any given count. The information is then time division multiplexed, providing one BCD number or digit at a time. Digit select outputs provide display control. All outputs are TTL compatible. An on­chip oscillator provides the low­frequency scanning clock which drives the multiplexer output selector. This device is used in instrumentation counters, clock displays, digital panel meters, and as a building block for general logic applications.

TTL Compatible Outputs On­Chip Oscillator Cascadable Clock Disable Input Pulse Shaping Permits Very Slow Rise Times on Input Clock Output Latches Master Reset

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)

Symbol VDD Vin, Vout Iin Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input Current (DC or Transient) per Pin Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 2.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8­Second Soldering) Value ­0.5 to VDD +150 260 Unit mA A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week

1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic "P and D/DW" Packages: ­ 7.0 mW/_C From To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

Inputs Master Reset X = Don't Care Clock Disable 1 LE Outputs No Change Advance No Change Advance No Change No Change Latched = 0

3. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 4. The formulas given are for the typical characteristics only 5. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL ­ 50) Vfk where: in µA (per package), CL in pF, V = (VDD ­ VSS) in volts, f in kHz is input frequency, and = 0.004.




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