|
|
Part: MC14562BCP
Category:
Logic
-> Registers
Description: 128-Bit Static Shift Register , Package: Pdip, Pins=14
Company: ON Semiconductor
Datasheet: Download MC14562BCP datasheet File size : 135 kB
Request For quote: Find where to buy MC14562BCP
Datasheet text preview:
MC14562B 128-Bit Static Shift Register
The MC14562B is a 128bit static shift register constructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. Data is clocked in and out of the shift register on the positive edge of the clock input. Data outputs are available every 16 bits, from 16 through bit 128. This complementary MOS shift register is primarily used where low power dissipation and/or high noise immunity is desired.
http://onsemi.com
· · · · ·
Diode Protection on All Inputs Fully Static Operation Cascadable to Provide Longer Shift Register Lengths Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Lowpower TTL Loads or One Lowpower Schottky TTL Load Over the Rated Temperature Range
A WL, L YY, Y WW, W
MARKING DIAGRAMS
14 PDIP14 P SUFFIX CASE 646 MC14562BCP AWLYYWW 1 = Assembly Location = Wafer Lot = Year = Work Week
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 2.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8Second Soldering) Value 0.5 to +18.0 0.5 to VDD + 0.5 ±10 500 55 to +125 65 to +150 260 Unit V V mA mW °C °C °C
ORDERING INFORMATION
Device MC14562BCP Package PDIP14 Shipping 25/Rail
1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic "P and D/DW" Packages: 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
© Semiconductor Components Industries, LLC, 2000
1
August, 2000 Rev. 4
Publication Order Number: MC14562B/D
MC14562B
PIN ASSIGNMENT
Q64 Q96 Q128 NC CLOCK Q112 VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD Q32 DATA NC Q16 Q48 Q80
NC = NO CONNECTION
BLOCK DIAGRAM
Q16 Q32 Q48 Q64 Q80 Q96 Q112 Q128 10 13 9 1 8 2 6 3
12
DATA
5
CLOCK
Pins 4 and 11 not used.
VDD = PIN 14 VSS = PIN 7
LOGIC DIAGRAM
CLOCK 5 DATA IN 12
DQ C 1
DQ C 2
DQ C 3
DQ C 16
DQ C 17
DQ C 32
DQ C 33
DQ C 48
DQ C 49
DQ C 64
10 Q16 DQ C 65 DQ C 80 DQ C 81 DQ C 96 DQ C 97 DQ C 112 DQ C 113 DQ C 128 13 Q32 9 Q48 1 Q64 8 Q80 2 Q96 6 Q112 3 Q128
http://onsemi.com
2
MC14562B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 3.0 0.64 1.6 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- ±0.1 -- 5.0 10 20 2.4 0.51 1.3 3.4 0.51 1.3 3.4 -- -- -- -- -- 4.2 0.88 2.25 8.8 0.88 2.25 8.8 ±0.00001 5.0 0.010 0.020 0.030 -- -- -- -- -- -- -- ±0.1 7.5 5.0 10 20 1.7 0.36 0.9 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- ±1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- 55_C 25_C 125_C Max Min -- -- -- Typ (3.) 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 05 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current (4.) (5.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Ci n IDD µAdc pF µAdc IT IT = (1.94 µA/kHz) f + IDD IT = (3.81 µA/kHz) f + IDD IT = (5.52 µA/kHz) f + IDD µAdc 3. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 4. The formulas given are for the typical characteristics only at 25_C. 5. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.004.
http://onsemi.com
3
Others parts begin by mc
|
|
|
