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Part: MC14569BCP
Category:
Logic
-> Counters
Description: Programmable Divide-by-n Dual 4-Bit Binary/bcd Down Counter , Package: Pdip, Pins=16
Company: ON Semiconductor
Datasheet: Download MC14569BCP datasheet File size : 291 kB
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Datasheet text preview:
MC14569B Programmable Divide-By-N Dual 4-Bit Binary/BCD Down Counter
The MC14569B is a programmable dividebyN dual 4bit binary or BCD down counter constructed with MOS Pchannel and Nchannel enhancement mode devices (complementary MOS) in a monolithic structure. This device has been designed for use with the MC14568B phase comparator/counter in frequency synthesizers, phaselocked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity.
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MARKING DIAGRAMS
16 PDIP16 P SUFFIX CASE 648 MC14569BCP AWLYYWW 1 16 TSSOP16 DT SUFFIX CASE 948F 1 16 14 569B ALYW
· Speedup Circuitry for Zero Detection · Each 4Bit Counter Can Divide Independently in BCD or Binary
Mode · Can be Cascaded With MC14526B for Frequency Synthesizer Applications · All Outputs are Buffered · Schmitt Triggered Clock Conditioning
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 2.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8Second Soldering) Value 0.5 to +18.0 0.5 to VDD + 0.5 ±10 500 55 to +125 65 to +150 260 Unit V V
SOIC16 DW SUFFIX CASE 751G 1
14569B
AWLYYWW
mA mW °C °C °C
A WL, L YY, Y WW, W
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device MC14569BCP MC14569BDT MC14569BDW MC14569BDWR2 Package PDIP16 TSSOP16 SOIC16 SOIC16 Shipping 2000/Box 96/Rail 47/Rail 1000/Tape & Reel
1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic "P and D/DW" Packages: 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
© Semiconductor Components Industries, LLC, 2000
1
August, 2000 Rev. 4
Publication Order Number: MC14569B/D
MC14569B
PIN ASSIGNMENT
ZERO DETECT CTL1 P0 P1 P2 P3 CASCADE FEEDBACK VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Q P7 P6 P5 P4 CTL2 CLOCK
BLOCK DIAGRAM
P0 P1 P2 P3 CTL = Low for Binary Count CTL = High for BCD Count 3 4 5 6 CTL1 CTL2 2 10 P4 P5 P6 P7 11 12 13 14 VDD = PIN 16 VSS = PIN 8 15 Q
CLOCK
9
BINARY/BCD COUNTER #1
CLOCK LOAD
BINARY/BCD COUNTER #2
CASCADE 7 FEEDBACK
ZERO DETECT ENCODER
1 ZERO DETECT
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MC14569B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 Min -- -- -- 55_C 25_C 125_C Max Min -- -- -- Typ (3.) 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 Vin = 0 or VDD "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- ±0.1 -- 5.0 10 20 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- ±0.1 7.5 5.0 10 20 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- ±1.0 -- 150 300 600 mAdc Vdc "1" Level VOH 4.95 9.95 14.95 -- -- -- 3.5 7.0 11 3.0 0.64 1.6 4.2 0.64 1.6 4.2 -- -- -- -- -- 4.95 9.95 14.95 -- -- -- 3.5 7.0 11 2.4 0.51 1.3 3.4 0.51 1.3 3.4 -- -- -- -- -- 5.0 10 15 2.25 4.50 6.75 2.75 5.50 8.25 4.2 0.88 2.25 8.8 0.88 2.25 8.8 ±0.00001 5.0 0.005 0.010 0.015 4.95 9.95 14.95 -- -- -- 3.5 7.0 11 1.7 0.36 0.9 2.4 0.36 0.9 2.4 -- -- -- -- -- Vdc Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) (VO = 0.5 or 4.5 Vdc) "1" Level (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current (4.) (5.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Source VIL Vdc IOH mAdc Sink Iin Ci n IDD µAdc pF µAdc IT IT = (0.58 µA/kHz) f + IDD IT = (1.20 µA/kHz) f + IDD IT = (1.95 µA/kHz) f + IDD µAdc 3. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 4. The formulas given are for the typical characteristics only at 25_C. 5. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001.
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