Details, datasheet, quote on part number: MC74HC03AN
PartMC74HC03AN
CategoryLogic => Gates
DescriptionQuad 2-Input NAND Gate With Drain , Package: Soic, Pins=14
CompanyON Semiconductor
DatasheetDownload MC74HC03AN datasheet
Cross ref.Similar parts: 74VHC03FT, 5962-8764701CA, SN74HC03N, CD74HC03E, M74HC03B1R, MC74HC03A, MC74HC03N
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Features, Applications
MC74HC03A Quad 2-Input NAND Gate with Open-Drain Outputs

The MC74HC03A is identical in pinout to the LS03. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC03A NAND gate has, as its outputs, a high­performance MOS N­Channel transistor. This NAND gate can, therefore, with a suitable pullup resistor, be used in wired­AND applications. Having the output characteristic curves given in this data sheet, this device can be used as an LED driver or in any other application that only requires a sinking current. Output Drive Capability: 10 LSTTL Loads With Suitable Pullup Resistor Outputs Directly Interface to CMOS, NMOS and TTL High Noise Immunity Characteristic of CMOS Devices Operating Voltage Range: to 6V Low Input Current: 1µA In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 28 FETs or 7 Equivalent Gates

Criteria Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product * Equivalent to a two­input NAND gate Value Unit µW pJ

PDIP­14 N SUFFIX CASE 646 MC74HC03AN AWLYYWW SOIC­14 D SUFFIX CASE TSSOP­14 DT SUFFIX CASE HC 03A ALYW HC03A AWLYWW

A = Assembly Location L = Wafer Lot Y = Year W = Work Week

Device MC74HC03ADR2 MC74HC03ADT Package SOIC­14 TSSOP­14 Shipping 2000 / Box 55 / Rail 2500 / Reel 96 / Rail 2500 / Reel

Symbol VCC Vin Parameter Value Unit V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) 0.5 to VCC to VCC Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature 150 260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package

Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: ­ 10 mW/_C from to 125_C SOIC Package: ­ 7 mW/_C from to 125_C TSSOP Package: ­ 6.1 mW/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D).

Symbol VIH Parameter Minimum High­Level Input Voltage

Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Maximum Three­State Leakage Current

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D).

Maximum Output Transition Time, Any Output (Figures 1 and 2)
Maximum Input Capacitance Maximum Three­State Output Capacitance (Output in High­Impedance State)

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC 5.0 V, VEE 0 V CPD Power Dissipation Capacitance (Per Buffer)* pF * Used to determine the no­load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D).


 

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