Details, datasheet, quote on part number: MC74HC138ADT
CategoryLogic => Multiplexers/Demultiplexers => Multiplexers
Description1-of-8 Decoder/demultiplexer , Package: Soic, Pins=16
CompanyON Semiconductor
DatasheetDownload MC74HC138ADT datasheet
Cross ref.Similar parts: SN74HC138PW, SN74HC138QPWRQ1, 74AC11138, CD4028B, CD4511B, CD4543B, CD4555B, CD4556B, CD74AC138, CD74AC139
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Features, Applications

The MC74HC138A is identical in pinout to the LS138. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC138A decodes a three­bit Address to one­of­eight active­low outputs. This device features three Chip Select inputs, two active­low and one active­high to facilitate the demultiplexing, cascading, and chip­selecting functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output; one of the Chip Selects is used as a data input while the other Chip Selects are held in their active states. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 6.0 V Low Input Current: 1.0 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 100 FETs or 29 Equivalent Gates

A0 ADDRESS INPUTS YY WW ACTIVE­LOW OUTPUTS = Assembly Location = Wafer Lot = Year = Work Week

Device MC74HC138ADT MC74HC138ADTR2 Package SOIC­16 TSSOP­16 Shipping 2000 / Box 48 / Rail 2500 / Reel 96 / Rail 2500 / Reel

H = high level (steady state); L = low level (steady state); X = don't care

Symbol VCC Vin Parameter Value Unit V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) 0.5 to VCC to VCC Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature 150 260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package)

Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 2) VCC

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: ­ 10 mW/_C from to 125_C SOIC Package: ­ 7 mW/_C from to 125_C TSSOP Package: ­ 6.1.W/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D).

Guaranteed Limit 85_C Symbol VOL Parameter Test Conditions VCC 125_C 0.1 Unit V Maximum Low­Level Output Voltage Vin = VIH or VIL |Iout| µA 0.1 Vin = VIH or VIL |Iout| Vin = VCC or GND Vin = VCC or GND Iout 5.2 mA Iin Maximum Input Leakage Current µA ICC Maximum Quiescent Supply Current (per Package) NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D).

Guaranteed Limit 85_C Symbol tPLH, tPHL Parameter VCC 25_C 125_C Unit ns Maximum Propagation Delay, Input A to Output Y (Figures 1 and tPLH, tPHL Maximum Propagation Delay, CS1 to Output Y (Figures 2 and 4) ns tPLH, tPHL Maximum Propagation Delay, CS3 to Output Y (Figures 3 and ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 2 and 4) ns Cin Maximum Input Capacitance pF NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC 5.0 V CPD Power Dissipation Capacitance (Per Package)* pF * Used to determine the no­load dynamic power consumption: CC V CC. For load considerations, see Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D).


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