Details, datasheet, quote on part number: MC74HC165AFR2
PartMC74HC165AFR2
CategoryLogic => Registers
Description8-Bit Serial or Parallel-input/serial Output Shift Register , Package: Soic, Pins=16
CompanyON Semiconductor
DatasheetDownload MC74HC165AFR2 datasheet
  

 

Features, Applications

The MC74HC165A is identical in pinout to the LS165. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device an 8­bit shift register with complementary outputs from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Serial Shift/Parallel Load input is low, the data is loaded asynchronously in parallel. When the Serial Shift/Parallel Load input is high, the data is loaded serially on the rising edge of either Clock or Clock Inhibit (see the Function Table). The 2­input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit.

Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 286 FETs or 71.5 Equivalent Gates

TSSOP­16 DT SUFFIX CASE A = Assembly Location L = Wafer Lot Y = Year W = Work Week HC 165A ALYW

Device MC74HC165ADT MC74HC165ADTR2 Package SOIC­16 TSSOP­16 Shipping 2000 / Box 48 / Rail 2500 / Reel 96 / Rail 2500 / Reel

A B PARALLEL DATA INPUTS C QH SERIAL DATA OUTPUTS
SERIAL SHIFT/ PARALLEL LOAD CLOCK PIN 16 = VCC PIN 8 = GND QH GND VCC CLOCK INHIBIT SA QH
H 6 SERIAL SA 10 DATA INPUT SERIAL SHIFT/ 1 PARALLEL LOAD CLOCK 2 CLOCK INHIBIT

Serial Shift/ Parallel Load Inputs Clock Inhibit Clock Internal Stages SA A­H a...h QB b QAn No Change No Change Output QH h QGn Operation Asynchronous Parallel Load Serial Shift via Clock Serial Shift via Clock Inhibit Inhibited Clock No Clock

Symbol VCC Vin Parameter Value Unit V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) 0.5 to VCC to VCC Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature 260 _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package)

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: ­ 10 mW/_C from to 125_C SOIC Package: ­ 7 mW/_C from to 125_C TSSOP Package: ­ 6.1 mW/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D).

Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC _C ns tr, tf VCC 2.0 V VCC 3.0 V VCC 4.5 V VCC 6.0 V


 

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