Details, datasheet, quote on part number: MC74HC175
CategoryLogic => Flip-Flops => CMOS/BiCMOS->HC/HCT Family
DescriptionQuad D Flip-flop With Common Clock & Reset
CompanyON Semiconductor
DatasheetDownload MC74HC175 datasheet
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Features, Applications

Quad D Flip-Flop with Common Clock and Reset

The MC54/74HC175 is identical in pinout to the LS175. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of four D flip­flops with common Reset and Clock inputs, and separate D inputs. Reset (active­low) is asynchronous and occurs when a low level is applied to the Reset input. Information a D input is transferred to the corresponding Q output on the next positive going edge of the Clock input. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity 166 FETs or 41.5 Equivalent Gates

Symbol VCC Vin Parameter Value Unit V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) 0.5 to VCC to VCC Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package Storage Temperature mW Tstg 65 to

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) (Ceramic DIP)

Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC

* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: ­ 10 mW/_C from to 125_C Ceramic DIP: ­ 10 mW/_C from to 125_C SOIC Package: ­ 7 mW/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D).

Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package)

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D).

Guaranteed Limit 85_C Symbol fmax Parameter VCC 20 24 Unit Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) Maximum Propagation Delay, Clock or Q (Figures 1 and MHz tPLH, tPHL ns Maximum Propagation Delay, Reset or Q (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Input Capacitance ns tTLH, tTHL Cin ns pF NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC 5.0 V CPD Power Dissipation Capacitance (Per Flip­Flop)* 35 pF

* Used to determine the no­load dynamic power consumption: PD = CPD VCC f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High­Speed CMOS Data Book (DL129/D).

Minimum Setup Time, Data to Clock (Figure 3) Minimum Hold Time, Clock to Data (Figure 3)
Minimum Recovery Time, Reset Inactive to Clock (Figure 2) Minimum Pulse Width, Clock (Figure 1)
Maximum Input Rise and Fall Times (Figure 1)


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