|Category||Logic => Flip-Flops|
|Description||Octal D-type Flip-flop , Package: Tssop, Pins=20|
|Datasheet||Download MC74HC374ADT datasheet
|Cross ref.||Similar parts: 74HC374PW, 74VHC374FT, SN74HC374PWR, 74AC16244, 74ACT16373, 74ACT16374, 74ACT16541, 74ACT16543, CD40109B, CD40109B-MIL|
The MC74HC374A is identical in pinout to the LS374. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Data meeting the setup time is clocked to the outputs with the rising edge of the clock. The Output Enable input does not affect the states of the flipflops, but when Output Enable is high, the outputs are forced to the highimpedance state; thus, data may be stored even when the outputs are not enabled. The HC374A is identical in function to the HC574A which has the input pins on the opposite side of the package from the output. This device is similar in function to the HC534A which has inverting outputs.
Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 6.0 V Low Input Current: 1.0 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 266 FETs or 66.5 Equivalent Gates= Assembly Location = Wafer Lot = Year = Work Week
Inputs Output Enable Clock Output L No Change Z
Device MC74HC374ADTR2 1 Package PDIP20 SOICWIDE TSSOP20 Shipping 1440 / Box 38 / Rail 1000 / Reel 75 / Rail 2500 / Reel
Symbol VCC Vin Parameter Value Unit V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) 0.5 to VCC to VCC Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature 150 260
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC, SSOP or TSSOP Package)
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: 10 mW/_C from to 125_C SOIC Package: 7 mW/_C from to 125_C TSSOP Package: 6.1 mW/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC
Guaranteed Limit 85_C Symbol VOL Parameter Test Conditions VCC 25_C 125_C Unit V Maximum LowLevel Output Voltage Vin = VIH or VIL |Iout| 20 µA Vin = VIH or VIL |Iout| Vin = VCC or GND mA V Iin Maximum Input Leakage Current Maximum ThreeState Leakage Current µA IOZ Output in HighImpedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout 0 µA ICC Maximum Quiescent Supply Current (per Package) µA NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit 85_C Symbol fmax Parameter VCC 25_C 125_C Unit Maximum Clock Frequency (50% Duty Cycle) MHz tPLH tPHL Maximum Propagation Delay, Input Clock to Q (Figures 1 and ns tPLZ tPHZ Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) ns tPLZ tPHZ Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) ns tTLH tTHL Maximum Output Transition Time, Any Output (Figures 1 and 5) ns Cin Maximum Input Capacitance pF Cout Maximum ThreeState Output Capacitance (Output in HighImpedance State) NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D). Typical @ 25°C, VCC 5.0 V CPD Power Dissipation Capacitance (Per Enabled Output)* pF * Used to determine the noload dynamic power consumption: CC V CC. For load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
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