Details, datasheet, quote on part number: MC74HC390ADR2
PartMC74HC390ADR2
CategoryLogic => Counters
DescriptionDual 4-Stage Binary Ripple Counter With Divide-By-2 And Divide-By-5 Sections , Package: Soic, Pins=16
CompanyON Semiconductor
DatasheetDownload MC74HC390ADR2 datasheet
Cross ref.Similar parts: 74HC390D, CD74HC390M96
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Features, Applications
MC74HC390A Dual 4-Stage Binary Ripple Counter with ÷ 2 and ÷ 5 Sections

The MC74HC390A is identical in pinout to the LS390. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two independent 4­bit counters, each composed of a divide­by­two and a divide­by­five section. The divide­by­two and divide­by­five counters have separate clock inputs, and can be cascaded to implement various combinations ÷ 2 and/or ÷ 100 counter. Flip­flops internal to the counters are triggered by high­to­low transitions of the clock input. A separate, asynchronous reset is provided for each 4­bit counter. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or strobes except when gated with the Clock of the HC390A. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No 7A Chip Complexity: 244 FETs or 61 Equivalent Gates

TSSOP­16 DT SUFFIX CASE WW = Assembly Location = Wafer Lot = Year = Work Week HC 390A ALYW
Clock Reset H L Action Reset ÷ 2 and ÷ 5 Increment ÷2 Increment ÷5

Device MC74HC390ADT MC74HC390ADTR2 Package SOIC­16 TSSOP­16 Shipping 2000 / Box 48 / Rail 2500 / Reel 96 / Rail 2500 / Reel

Symbol VCC Vin Parameter Value Unit V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) 0.5 to VCC to VCC Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature 150 260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package

Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: ­ 10 mW/_C from to 125_C SOIC Package: ­ 7 mW/_C from to 125_C TSSOP Package: ­ 6.1 mW/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D).


Guaranteed Limit 85_C Symbol Iin Parameter Test Conditions VCC 4 125_C Unit µA Maximum Input Leakage Current Vin = VCC or GND Vin = VCC or GND Iout 0 µA ICC Maximum Quiescent Supply Current (per Package) NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D).

Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 3)

Maximum Propagation Delay, Clock to QC (QA connected to Clock B) (Figures 1 and 3) Maximum Propagation Delay, Clock to QB (Figures 1 and 3)

Maximum Output Transition Time, Any Output (Figures 1 and 3)

Cin Maximum Input Capacitance pF 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC 5.0 V CPD Power Dissipation Capacitance (Per Counter)* 35 pF

* Used to determine the no­load dynamic power consumption: CC V CC. For load considerations, see Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D).


 

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