Details, datasheet, quote on part number: MC74HC393ADR2
PartMC74HC393ADR2
CategoryLogic => Counters
DescriptionDual 4-Stage Binary Ripple Counter , Package: Soic, Pins=14
CompanyON Semiconductor
DatasheetDownload MC74HC393ADR2 datasheet
Cross ref.Similar parts: 74HC393D, SN74HC393D, CD40102B, CD40103B, CD4017B, CD4017B-MIL, CD4020B, CD4020B-MIL, CD4040B, CD4060B
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Features, Applications

The MC74HC393A is identical in pinout to the LS393. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two independent 4­bit binary ripple counters with parallel outputs from each counter stage. ÷ 256 counter can be obtained by cascading the two binary counters. Internal flip­flops are triggered by high­to­low transitions of the clock input. Reset for the counters is asynchronous and active­high. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or as strobes except when gated with the Clock of the HC393A.

PDIP­14 N SUFFIX CASE 646 MC74HC393AN AWLYYWW SOIC­14 D SUFFIX CASE TSSOP­14 DT SUFFIX CASE HC 393A ALYW HC393A AWLYWW

Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 236 FETs or 59 Equivalent Gates

A = Assembly Location L = Wafer Lot Y = Year W = Work Week

3, 11 CLOCK BINARY COUNTER PIN 14 = VCC PIN 7 = GND Q3 Q4 CLOCK a RESET Q1a Q2a RESET Q3a Q4a GND VCC CLOCK b RESET Q3b Q4b

Inputs Clock H L Reset Outputs L No Change No Change No Change Advance to Next State

Device MC74HC393ADT MC74HC393ADTR2 Package SOIC­14 TSSOP­14 Shipping 2000 / Box 55 / Rail 2500 / Reel 96 / Rail 2500 / Reel

Symbol VCC Vin Parameter Value Unit V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) 0.5 to VCC to VCC Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature 150 260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: ­ 10 mW/_C from to 125_C SOIC Package: ­ 7 mW/_C from to 125_C TSSOP Package: ­ 6.1 mW/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D).

Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC


Guaranteed Limit 85_C Symbol VOL Parameter Test Conditions VCC 125_C 0.1 Unit V Maximum Low­Level Output Voltage Vin = VIH or VIL |Iout| µA 0.1 Vin = VIH or VIL |Iout| Vin = VCC or GND Vin = VCC or GND Iout 5.2 mA Iin Maximum Input Leakage Current µA ICC Maximum Quiescent Supply Current (per Package) NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D).

Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 3)
Maximum Output Transition Time, Any Output (Figures 1 and 3)

NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D).


 

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