Details, datasheet, quote on part number: MC74HC4040ADR2
PartMC74HC4040ADR2
CategoryLogic => Counters
DescriptionMonolithic Wfr, Binary Counter , Package: Soic, Pins=16
CompanyON Semiconductor
DatasheetDownload MC74HC4040ADR2 datasheet
Cross ref.Similar parts: 74HC4040D, CD74HC4040M96, CD40102B, CD40103B, CD4017B, CD4017B-MIL, CD4020B, CD4020B-MIL, CD4040B, CD4060B
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Features, Applications

The MC74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of 12 master­slave flip­flops. The output of each flip­flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative­going edge of the Clock input. Reset is asynchronous and active­high. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs.

Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance With JEDEC Standard No. 7A Requirements Chip Complexity: 398 FETs or 99.5 Equivalent Gates

TSSOP­16 DT SUFFIX CASE WW = Assembly Location = Wafer Lot = Year = Work Week HC40 40A ALYW
Clock Reset L H Output State No Charge Advance to Next State All Outputs Are Low

Device Q1 9 Package SOIC­16 TSSOP­16 Shipping 2000 / Box 48 / Rail 2500 / Reel 96 / Rail 2500 / Reel

Symbol VCC Vin Parameter Value Unit V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) 0.5 to VCC to VCC Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature Range 260 _C Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: ­ 10 mW/_C from to 125_C SOIC Package: ­ 7 mW/_C from to 125_C TSSOP Package: ­ 6.1 mW/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D).

Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature Range, All Package Types Input Rise and Fall Time (Figure 1) VCC _C ns tr, tf VCC 2.0 V VCC 3.0 V VCC 4.5 V VCC 6.0 V

Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package)

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D).

Parameter Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4)
Maximum Output Transition Time, Any Output (Figures 1 and 4)

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D). * For = 25°C and = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations: VCC (n­1)] ns VCC (n­1)] ns VCC (n­1)] ns VCC (n­1)] ns Typical @ 25°C, VCC 2 * Used to determine the no­load dynamic power consumption: PD = CPD VCC f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D). CPD Power Dissipation Capacitance (Per Package)*


 

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