Details, datasheet, quote on part number: MC74HC4046A
CategoryCommunication => Freq/Signal Converters/Generators
DescriptionPhase-locked-loop With Vco
CompanyON Semiconductor
DatasheetDownload MC74HC4046A datasheet
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Features, Applications

The MC74HC4046A is similar in function to the MC14046 Metal gate CMOS device. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC4046A phase­locked loop contains three phase comparators, a voltage­controlled oscillator (VCO) and unity gain op­amp DEMOUT. The comparators have two common signal inputs, COMP IN, and SIG IN. Input SIG IN and COMP IN can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor to small voltage signals). The self­bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error signal PC1 OUT and maintains 90 degrees phase shift at the center frequency between SIG IN and COMP IN signals (both at 50% duty cycle). Phase comparator 2 (with leading­edge sensing logic) provides digital error signals PC2 OUT and PCP OUT and maintains a 0 degree phase shift between SIG IN and COMP IN signals (duty cycle is immaterial). The linear VCO produces an output signal VCOOUT whose frequency is determined by the voltage of input VCO IN signal and the capacitor and resistors connected to pins C1B, R1 and R2. The unity gain op­amp output DEMOUT with an external resistor is used where the VCO IN signal is needed but no loading can be tolerated. The inhibit input, when high, disables the VCO and all op­amps to minimize standby power consumption. Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltage­to­frequency conversion and motor speed control.

Output Drive Capability: 10 LSTTL Loads Low Power Consumption Characteristic of CMOS Devices Operating Speeds Similar to LSTTL Wide Operating Voltage Range: 6.0 V Low Input Current: 1.0 µA Maximum (except SIGIN and COMPIN) In Compliance with the Requirements Defined by JEDEC Standard No. 7A Low Quiescent Current: 80 µA Maximum (VCO disabled) High Noise Immunity Characteristic of CMOS Devices Diode Protection on all Inputs Chip Complexity: 279 FETs or 70 Equivalent Gates

= Assembly Location = Wafer Lot = Year = Work Week

Device MC74HC4046ADR2 MC74HC4046AF Package PDIP­16 SOIC­16 SOIC­EIAJ Shipping 2000 / Box 48 / Rail 2500 / Reel

See Note NO TAG MC74HC4046AFEL SOIC­EIAJ See Note NO TAG 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.

Pin No. Symbol PCPOUT PC1OUT COMPIN VCOOUT INH C1A C1B GND VCOIN DEMOUT R2 PC2OUT SIGIN PC3OUT VCC Name and Function Phase Comparator Pulse Output Phase Comparator 1 Output Comparator Input VCO Output Inhibit Input Capacitor C1 Connection A Capacitor C1 Connection B Ground (0 V) VSS VCO Input Demodulator Output Resistor R1 Connection Resistor R2 Connection Phase Comparator 2 Output Signal Input Phase Comparator 3 Output Positive Supply Voltage

PCPout PC1out COMPin VCOout INH C1A C1B GND VCC PC3out SIGin R2 R1 DEMout VCOin

Symbol VCC Vin Parameter Value Unit V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) 0.5 to VCC to VCC Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Plastic DIP SOIC Package mW Tstg 150 260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP and SOIC Package

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: ­ 10 mW/_C from to 125_C SOIC Package: ­ 7 mW/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D).

Symbol VCC Parameter Min 3.0 Max 6.0 Unit V DC Supply Voltage (Referenced to GND) VCC DC Supply Voltage (Referenced to GND) NON­VCO 6.0 V Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Pin 5) VCC V

[Phase Comparator Section] DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit Symbol VIH Parameter Minimum High­Level Input Voltage DC Coupled SIGIN, COMPIN Maximum Low­Level Input Voltage DC Coupled SIGIN, COMPIN Minimum High­Level Output Voltage PCPOUT, PCnOUT Test Conditions Vout V or VCC 0.1 V |Iout| 20 µA Vout V or VCC 0.1 V |Iout| 20 µA Vin = VIH or VIL |Iout| 20 µA Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA VCC Volts 85°C 125°C (continued) Unit V

[Phase Comparator Section] DC ELECTRICAL CHARACTERISTICS ­ continued (Voltages Referenced to GND)

Guaranteed Limit Symbol VOL Parameter Maximum Low­Level Output Voltage Qa­Qh PCPOUT, PCnOUT Test Conditions Vout V or VCC 0.1 V |Iout| 20 µA Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA Iin Maximum Input Leakage Current SIGIN, COMPIN Maximum Three­State Leakage Current PC2OUT Maximum Quiescent Supply Current (per Package) (VCO disabled) Pins 3, 5 and 14 at VCC Pin 9 at GND; Input Leakage at Pins 3 and to be excluded Vin = VCC or GND VCC Volts 125°C µA Unit V

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D).

[Phase Comparator Section] AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input = 6.0 ns)

Symbol tPLH, tPHL tPLH, tPHL Parameter Maximum Propagation Delay, SIGIN/COMPIN to PC1OUT (Figure 1) Maximum Propagation Delay, SIGIN/COMPIN to PCPOUT (Figure 1) VCC Volts Guaranteed Limit 85°C 125°C Unit ns


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