Details, datasheet, quote on part number: MC74HC4053AFL1
PartMC74HC4053AFL1
CategoryLogic => Analog Switches/Multiplexers => Analog Switches
TitleAnalog Switches
DescriptionAnalog Multiplexers / Demultiplexers , Package: Soic, Pins=16
CompanyON Semiconductor
DatasheetDownload MC74HC4053AFL1 datasheet
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Features, Applications

The MC74HC4051A, MC74HC4052A and MC74HC4053A utilize silicon­gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The HC4051A, HC4052A and HC4053A are identical in pinout to the metal­gate MC14051AB, MC14052AB and MC14053AB. The Channel­Select inputs determine which one of the Analog Inputs/Outputs to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off. The Channel­Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors they are compatible with LSTTL outputs. These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal­gate CMOS analog switches. For a multiplexer/demultiplexer with injection current protection, see HC4851A and HC4852A. Fast Switching and Propagation Speeds Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Analog Power Supply Range (VCC ­ VEE) 12.0 V Digital (Control) Power Supply Range (VCC ­ GND) 6.0 V Improved Linearity and Lower ON Resistance Than Metal­Gate Counterparts Low Noise In Compliance With the Requirements of JEDEC Standard No. 7A Chip Complexity: HC4051A 184 FETs or 46 Equivalent Gates HC4052A 168 FETs or 42 Equivalent Gates HC4053A 156 FETs or 39 Equivalent Gates

= Assembly Location = Wafer Lot = Year = Work Week

See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet.

FUNCTION TABLE ­ MC74HC4051A LOGIC DIAGRAM MC74HC4051A Single­Pole, 8­Position Plus Common Off

15 X2 ANALOG 12 MULTIPLEXER/ INPUTS/ X3 DEMULTIPLEXER OUTPUTS 11 A CHANNEL 10 B SELECT 9 INPUTS C 6 ENABLE PIN 16 = VCC PIN 7 = VEE PIN 8 = GND

Control Inputs Enable Select ON Channels X6 X7 NONE X = Don't Care
FUNCTION TABLE ­ MC74HC4052A LOGIC DIAGRAM MC74HC4052A Double­Pole, 4­Position Plus Common Off
Control Inputs Select Enable Don't Care ON Channels Y2 Y3 NONE X2 X3

FUNCTION TABLE ­ MC74HC4053A LOGIC DIAGRAM MC74HC4053A Triple Single­Pole, Double­Position Plus Common Off

Control Inputs Enable Select ON Channels Y0 Y1 NONE X0 X1

NOTE: This device allows independent control of each switch. Channel­Select Input A controls the X­Switch, Input B controls the Y­Switch and Input C controls the Z­Switch

Symbol VCC VEE VIS Vin I Parameter Value Unit Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE) + 5.0 VEE 0.5 to VCC Negative DC Supply Voltage (Referenced to GND) Analog Input Voltage Digital Input Voltage (Referenced to GND) DC Current, Into or Out of Any Pin Power Dissipation in Still Air, 0.5 to VCC mA PD Plastic DIP EIAJ/SOIC Package TSSOP Package mW Tstg TL Storage Temperature Range 150 260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: ­ 10 mW/_C from to 125_C EIAJ/SOIC Package: ­ 7 mW/_C from to 125_C TSSOP Package: ­ 6.1 mW/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D).


 

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