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Details, datasheet, quote on part number:NB100EP223FAR2
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| Part: | NB100EP223FAR2 |
| Category: | Timing Circuits => Clock Distribution |
| Description: | 3.3V 1:22 Differential Hstl/pecl to HSTL Clock Driver With LVTTL Clock Select And Output Enable, Package: 64 Lead Exposed Pad Lqfp, Pins=64 |
| Company: | ON Semiconductor |
| Datasheet: | Download NB100EP223FAR2 datasheet File size : 97 kB |
| Request For quote: | Find where to buy NB100EP223FAR2
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Datasheet text preview:
NB100EP223 3.3V 1:22 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Output Enable
The NB100EP223 is a low skew 1-to-22 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are differential HSTL or LVPECL and they are selected by the CLK_SEL pin which is LVTTL. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable (OE), which is LV T T L , is synchronous ensuring the outputs will only be enabled/disabled when they are already in LOW state (See Figure 7). The NB100EP223 guarantees low output-to-output skew. The optimal design, layout, and processing minimize skew within a device and from lot to lot. In any differential output pair, the same bias and termination scheme is required. Unused output pairs should be left unterminated (open) to "reduce power and switching noise as much as possible." Any unused single line of a differential pair should be terminated the same as the used line to maintain balanced loads on the differential driver outputs. The output structure uses an open emitter architecture and will be terminated with 50 W to ground instead of a standard HSTL configuration (See Figure 6). The wide VIHCMR specification allows both pair of CLOCK inputs to accept LVDS levels.
http://onsemi.com MARKING DIAGRAM*
64
1 64 1
NB100 EP223 AWLYYWW
64-LEAD LQFP CASE 848G THERMALLY ENHANCED FA SUFFIX A WL YY WW
= Assembly Location = Wafer Lot = Year = Work Week
*For additional information, see Application Note AND8002/D
· 100 ps Typical Device-to- Device Skew · 25 ps Typical Within Device Skew · HSTL Compatible Outputs Drive 50 W to Ground With No
Offset Voltage · Maximum Frequency >500 MHz
ORDERING INFORMATION
Device NB100EP223FA NB100EP223FAR2 Package LQFP-64 Shipping 160 Units/Tray
· 1 ns Typical Propagation Delay · LVPECL and HSTL Mode Operating Range: VCC = 3 V to 3.6 V
with GND = 0 V, VCCO = 1.6 V to 2.0 V · Q Output will Default Low with Inputs Open
LQFP-64 1500/Tape & Reel
· Thermally Enhanced 64-Lead LQFP · CLOCK Inputs are LVDS-Compatible; Requires External 100 W
LVDS Termination Resistor
© Semiconductor Components Industries, LLC, 2003
1
June, 2003 - Rev. 5
Publication Order Number: NB100EP223/D
NB100EP223
VCCO VCCO 33 32 31 30 29 28 27 26 25 VCC0 Q14 Q14 Q15 Q15 Q16 Q16 Q17 Q17 Q18 Q18 Q19 Q19 Q20 Q20 VCC0 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VCC0 Q0-Q21 Q21 Q10 Q10 Q12 Q12 Q13 35 NC Q21 Q13 34
Q11 39
VCC0 Q6 Q6 Q5 Q5 Q4 Q4 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 VCC0
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
47
46
45
44
43
42
41
40
38
Q11
Q7
Q7
Q8
Q8
Q9
Q9
37
36
NB100EP223
HSTL_CLK
VCC0
VCC
NC
NC
LVPECL_CLK
LVPECL_CLK
HSTL_CLK
CLK_SEL
All VCC, VCCO, and GND pins must be externally connected to appropriate Power Supply to guarantee proper operation (VCC 0 VCCO). The thermally conductive exposed pad on package bottom (see package case drawing) is electrically connected to GND internally.
Figure 1. 64-Lead LQFP Pinout (Top View) PIN DESCRIPTION
PIN HSTL_CLK*, HSTL_CLK** LVPECL_CLK*, LVPECL_CLK** CLK_SEL** OE** Q0-Q21, Q0-Q21 VCC VCCO GND*** FUNCTION
GND
OE
FUNCTION TABLE
OE* CLK_SEL Q0-Q21
HSTL, LVPECL or LVDS Differential Inputs L L L H LVPECL Differential Inputs L H L H LVCMOS/LVTTL Input CLK Select H L HSTL_CLK HSTL_CLK LVCMOS/LVTTL Output Enable H H LVPECL_CLK LVPECL_CLK HSTL Differential Outputs Positive Supply_Core (3.0 V - 3.6 V) * The OE (Output Enable) signal is synchronized with the Positive Supply_HSTL Outputs(1.6V-2.0V) rising edge of the HSTL_CLK and LVPECL_CLK signal. Ground
* Pins will default LOW when left open. ** Pins will default HIGH when left open. *** The thermally conductive exposed pad on the bottom of the package is electrically connected to GND internally.
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NC
NB100EP223
CLK_SEL
HSTL_CLK HSTL_CLK LVPECL_CLK LVPECL_CLK VCC GND
0 22 22 1 Q OE D VCCO Q0-Q21 (HSTL) Q0-Q21 (HSTL)
Figure 2. Logic Diagram
ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW 37.5 kW > 2 kV > 150 V > 2 kV Level 3 Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in 693
Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, refer to Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol VCC VCCO VI Iout TA Tstg qJ A qJ C Tsol Parameter Core Power Supply HSTL Output Power Supply PECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (See Application Information) Thermal Resistance (Junction-to-Case) (See Application Information) Wave Solder 0 LFPM 500 LFPM 0 LFPM 500 LFPM < 2 to 3 sec @ 248°C 64 LQFP 64 LQFP 64 LQFP 64 LQFP Condition 1 GND = 0 V GND = 0 V GND = 0 V Continuous Surge Condition 2 VCCO = 1.8 V VCC = 3.3 V VI VCC Rating 4 4 4 50 100 0 to +85 -65 to +150 35.6 30 3.2 6.4 265 Units V V V mA mA °C °C °C/W °C/W °C/W °C/W °C
2. Maximum Ratings are those values beyond which device damage may occur.
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