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Details, datasheet, quote on part number:NB100LVEP221FA
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Datasheet text preview:
NB100LVEP221 2.5V/3.3V 1:20 Differential HSTL/ECL/PECL Clock Driver
The NB100LVEP221 is a low skew 1-to-20 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential ECL/PECL; CLK1/CLK1 can also receive HSTL signal levels. The LVPECL input signals can be either differential configuration or single-ended (if the VBB output is used). The LVEP221 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure tightest skew, both sides of differential outputs should be terminated identically into 50 W even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. The NB100LVEP221, as with most other ECL devices, can be operated from a positive VCC supply in LVPECL mode. This allows the LVEP221 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For more information on PECL terminations, designers should refer to Application Note AND8020/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single- ended LVPECL input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Single- ended CLK input operation is limited to a VCC 3.0 V in LVPECL mode, or VEE -3.0 V in NECL mode.
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NB100 LVEP221 AWLYYWW 52-LEAD LQFP THERMALLY ENHANCED CASE 848H FA SUFFIX A WL YY WW
52 1
= Assembly Location = Wafer Lot = Year = Work Week
*For additional information, refer to Application Note AND8002/D
ORDERING INFORMATION
Device NB100LVEP221FA NB100LVEP221FAR2 Package LQFP-52 Shipping 160 Units/Tray
· · · · · · · ·
15 ps Typical Output-to-Output Skew 40 ps Typical Device-to- Device Skew Jitter Less than 2 ps RMS Maximum Frequency > 1.0 GHz Typical Thermally Enhanced 52-Lead LQFP VBB Output 540 ps Typical Propagation Delay LVPECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V · NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V · Q Output will Default Low with Inputs Open or at VEE · Pin Compatible with Motorola MC100EP221
LQFP-52 1500/Tape & Reel
© Semiconductor Components Industries, LLC, 2003
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January, 2003 - Rev. 4
Publication Order Number: NB100LVEP221/D
NB100LVEP221
VCC0 27 26 25 24 23 22 21 Q12 Q12 Q13 Q13 Q14 Q14 Q15 Q15 Q16 Q16 Q17 Q17 VCC0 20 19 18 17 16 15 14 1 2 3 4 5 6 7 8 9 10 11 12 13 0 CLK0 CLK1 1 CLK1 VBB CLK_SEL VCC VEE 20 Q0 - Q19 Q0 - Q19 20 Q18 Q10 Q10 Q11 29 Q19 Q11 28 Q18 Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9
39 VCC0 Q5 Q5 Q4 Q4 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 40 41 42 43 44 45 46 47 48 49 50 51 52
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37
36
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34
33
32
31
30
NB100LVEP221
CLKSEL
CLK0
CLK1
CLK0
CLK1
VCC0
VCC
All VCC, VCCO, and VEE pins must be externally connected to appropriate Power Supply to guarantee proper operation. The thermally conductive exposed pad on package bottom (see package case drawing) must be attached to a heat-sinking conduit, capable of transferring 1.2 Watts. This exposed pad is electrically connected to VEE internally.
Figure 1. 52-Lead LQFP Pinout (Top View) PIN DESCRIPTION
PIN CLK0*, CLK0** CLK1*, CLK1** Q0:19, Q0:19 CLK_SEL* VBB VCC/VCCO VEE*** FUNCTION ECL/PECL Differential Inputs ECL/PECL or HSTL Differential Inputs ECL/PECL Differential Outputs ECL/PECL Active Clock Select Input Reference Voltage Output Positive Supply Negative Supply CLK0
* Pins will default LOW when left open. ** Pins will default HIGH when left open. *** The thermally conductive exposed pad on the bottom of the package is electrically connected to VEE internally.
FUNCTION TABLE
CLK_SEL L H Active Input CLK0, CLK0 CLK1, CLK1
Figure 2. Logic Diagram
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Q19
VBB
VEE
NB100LVEP221
ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Oxygen Index: 28 to 34 Value 75 kW 37.5 kW > 2 kV > 200 V > 2 kV Level 3 UL 94 V-0 @ 0.125 in 533 Devices
Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, refer to Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI Iout IBB TA Tstg qJ A qJ C Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (See Application Information) Thermal Resistance (Junction-to-Case) (See Application Information) Wave Solder 0 LFPM 500 LFPM 0 LFPM 500 LFPM < 2 to 3 sec @ 248°C 52 LQFP 52 LQFP 52 LQFP 52 LQFP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 ± 0.5 -40 to +85 -65 to +150 35.6 30 3.2 6.4 265 Units V V V V mA mA mA °C °C °C/W °C/W °C/W °C/W °C
2. Maximum Ratings are those values beyond which device damage may occur.
LVPECL DC CHARACTERISTICS VCC = 2.5 V; VEE = 0 V (Note 3)
-40 °C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage (Single-Ended) (Note 5) Input LOW Voltage (Single-Ended) (Note 5) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 6) CLK0/CLK0 CLK1/CLK1 Input HIGH Current Input LOW Current CLK CLK 0.5 -150 Min 100 1355 555 1335 555 Typ 125 1480 680 Max 150 1605 900 1620 900 Min 104 1355 555 1335 555 25°C Typ 130 1480 680 Max 156 1605 900 1620 900 Min 116 1355 555 1275 555 85°C Typ 145 1480 680 Max 174 1605 900 1620 900 Unit mA mV mV mV mV
1.2 0.3
2.5 1.6 150
1.2 0.3
2.5 1.6 150
1.2 0.3
2.5 1.6 150
V V mA mA
IIH IIL NOTE: 3. 4. 5. 6.
0.5 -150
0.5 -150
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.125 V to -1.3 V. All outputs loaded with 50 W to VCC - 2.0 V. Do not use VBB at VCC < 3.0 V. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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