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Details, datasheet, quote on part number:NB100LVEP222FAR2
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Datasheet text preview:
NB100LVEP222 2.5V/3.3V 1:15 Differential ECL/PECL ÷1/÷2 Clock Driver
The NB100LVEP222 is a low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be used in a differential configuration or single-ended (with VBB output reference bypassed and connected to the unused input of a pair). Either of two fully differential clock inputs may be selected. Each of the four output banks of 2, 3, 4, and 6 differential pairs may be independently configured to fanout 1X or 1/2X of the input frequency. The LVEP222 specifically guarantees low output to output skew. Optimal design, layout, and processing minimize skew within a device and from lot to lot. This device is an improved version of the MC100LVE222 with higher speed capability and reduced skew. The fsel pins and CLK_Sel pin are asynchronous control inputs. Any changes may cause indeterminate output states requiring an MR pulse to resynchronize any 1/2X outputs (See Figure 3). Unused output pairs should be left unterminated (open) to reduce power and switching noise. The NB100LVEP222, as with most ECL devices, can be operated from a positive VCC supply in LVPECL mode. This allows the LVEP222 to be used for high performance clock distribution in +2.5/3.3 V systems. In a PECL environment series or Thevenin line, terminations are typically used as they require no additional power supplies. For more information on using PECL, designers should refer to Application Note AN1406/D. For a SPICE model, refer to Application Note AN1560/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single- ended LVPECL input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Single- ended CLK input operation is limited to a VCC 3.0 V in LVPECL mode, or VEE v -3.0 V in NECL mode.
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MARKING DIAGRAM*
NB100 LVEP222 AWLYYWW 52-LEAD LQFP THERMALLY ENHANCED CASE 848H FA SUFFIX A WL YY WW
52 1
= Assembly Location = Wafer Lot = Year = Work Week
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device NB100LVEP222FA Package LQFP-52 Shipping 160 Units/Tray
NB100LVEP222FAR2 LQFP-52 1500/Tape & Reel
· · · ·
20 ps Output-to-Output Skew 85 ps Part-to-Part Skew Selectable 1x or 1/2x Frequency Outputs
LVPECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V · NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V · Internal Input Pulldown Resistors
· Performance Upgrade to ON Semiconductor's MC100LVE222 · VBB Output
© Semiconductor Components Industries, LLC, 2003
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January, 2003- Rev. 8
Publication Order Number: NB100LVEP222/D
NB100LVEP222
VCC0
VCC0
VCC0 Qb2 Qb2 Qb1 Qb1 Qb0 Qb0 VCC0 Qa1 Qa1 Qa0 Qa0 VCC0
39 40 41 42 43 44 45 46 47 48 49 50 51 52 1
38
37
36
35
34
33
32
31
30
29
28
VCC0 27 26 25 24 23 22 21
Qc0
Qc0
Qc1
Qc1
Qc2
Qc2
Qc3
Qc3
NC
NC
Qd0 Qd0 Qd1 Qd1 Qd2 Qd2 Qd3 Qd3 Qd4 Qd4 Qd5 Qd5 VCC0
NB100LVEP222
20 19 18 17 16 15 14
2
3
4
5
6
7
8
9
10
11
12
13
CLK0
CLK0
MR
CLK1
CLK_Sel
CLK1
fsela
fselb
fselc
fseld L Active CLK0 ÷1
VBB
All VCC, VCCO, and VEE pins must be externally connected to appropriate Power Supply to guarantee proper operation. The thermally conductive exposed pad on package bottom (see package case drawing) must be attached to a heat-sinking conduit. This exposed pad is electrically connected to VEE internally.
VCC
Figure 1. 52-Lead LQFP Pinout (Top View) PIN DESCRIPTION
PIN CLK0*, CLK0** CLK1*, CLK1** CLK_Sel* MR* Qa0:1, Qa0:1 Qb0:2, Qb0:2 Qc0:3, Qc0:3 Qd0:5, Qd0:5 fseln* VBB VCC, VCCO VEE*** NC FUNCTION ECL Differential Input Clock ECL Differential Input Clock ECL Clock Select ECL Master Reset ECL Differential Outputs ECL Differential Outputs ECL Differential Outputs ECL Differential Outputs ECL 1 or 2 Select Reference Voltage Output Positive Supply Negative Supply No Connect Input MR CLK_Sel fseln
FUNCTION TABLE
Function H Reset CLK1 ÷2
* Pins will default LOW when left open. ** Pins will default HIGH when left open. *** The thermally conductive exposed pad on the bottom of the package is electrically connected to VEE internally.
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VEE
NB100LVEP222
MR CLK0 CLK0 ÷1 CLK1 CLK1 ÷2 2 Qa0:1 Qa0:1
CLK_SEL
VBB fsela 3 Qb0:2 Qb0:2 fselb 4 VCC VEE Qc0:3 Qc0:3 fselc 6 Qd0:5 Qd0:5 fseld
Figure 2. Logic Diagram
CLK
MR
Q (B2)
Q (B1)
Figure 3. Master Reset (MR) Timing Diagram
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