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Details, datasheet, quote on part number:NBSG111BAR2
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| Part: | NBSG111BAR2 |
| Category: | Timing Circuits => Clock Distribution |
| Description: | 2.5 V/3.3 V Sige 1:10 Differential Clock Driver With Rsecl Outputs , Package: FCBGA-49, Pins=49 |
| Company: | ON Semiconductor |
| Datasheet: | Download NBSG111BAR2 datasheet File size : 89 kB |
| Request For quote: | Find where to buy NBSG111BAR2
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Datasheet text preview:
NBSG111 2.5V/3.3V SiGe Differential 1:10 Clock/Data Driver with RSECL* Outputs
*Reduced Swing ECL
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The NBSG111 is a 1-to-10 differential clock/data driver. The device is functionally equivalent to the LVEP111 device with much higher bandwidth and lower EMI capabilities. Inputs incorporate internal 50 W termination resistors (input to VT pad) and accept NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV. The Q[0:9] / Q[0:9] outputs have a differential synchronous enable (EN/EN) pin. The synchronous enable pin is used to avoid a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of selected clock (CLK0/CLK0 or CLK1/CLK1), therefore all associated specification limits are referenced to the negative edge of the selected clock input. The VBB and VMM pins are internally generated voltage supplies available to this device only. The VBB is used for single-ended NECL or PECL inputs and the VMM pin is used for LVCMOS inputs. For single- ended input operation, the unused differential input is connected to VBB or VMM as a switching reference voltage. VBB or VMM may also rebias AC coupled inputs. When used, decouple VBB and VMM via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB and VMM outputs should be left open.
MARKING DIAGRAM*
SG 111 LYW FCBGA-49 BA SUFFIX CASE 489A SG111 L Y W = Device Code = Wafer Lot = Year = Work Week
*For further details, refer to Application Note AND8002/D
ORDERING INFORMATION
Device NBSG111BA NBSG111BAR2 Package 8x8 mm FCBGA-49 8x8 mm FCBGA-49 Shipping 100 Units/Tray 500/Tape & Reel
· Maximum Input Clock Frequency > 6 GHz Typical · · · ·
Maximum Input Data Rate > 6 Gb/s Typical 300 ps Typical Propagation Delay 60 ps Typical Rise and Fall Times
RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V · RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V · RSECL Output Level (400 mV Peak-to-Peak Output), Differential Output · 50 W Internal Input Termination Resistors
Board NBSG111BAEVB
Description NBSG111BA Evaluation Board
· Compatible with Existing 2.5 V/3.3 V LVEP and EP Devices · VBB and VMM Reference Voltage Output
© Semiconductor Components Industries, LLC, 2003
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May, 2003 - Rev. 7
Publication Order Number: NBSG111/D
NBSG111
1 2 3 4 5 6 7
A
VEE
Q9
Q9
Q8
Q8
Q7
VEE
B
Q0
VMM
CLK1
CLK1
VCC
NC
Q7
C
Q0
VEE
VTCLK1
VTCLK1
VTSEL
SEL
Q6
D
Q1
EN
VTEN
VCC
VTSEL
SEL
Q6
E
Q1
EN
VTEN
VTCLK0
VTCLK0
VEE
Q5
F
Q2
NC
VCC
CLK0
CLK0
VBB
Q5
G
VEE
Q2
Q3
Q3
Q4
Q4
VEE
Figure 1. BGA-49 Pinout (Top View)
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NBSG111
Table 1. Pin Description
Pin A1,A7,G1,G7,C2,E6 F3,D4,B5 B2 F6 E4 F4 E5 F5 C4 B4 C3 B3 B1,D1,F1,G3,G5,F7, D7,B7,A5,A3 C1,E1,G2,G4,G6,E7, C7,A6,A4,A2 D5 D6 C5 C6 D3 D2 E3 E2 F2,B6 Name VEE VCC VMM VBB VTCLK0 CLK0 VTCLK0 CLK0 VTCLK1 CLK1 VTCLK1 CLK1 Q[0:9] Q[0:9] VTSEL SEL VTSEL SEL VTEN EN VTEN EN NC I/O ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input RSECL Output RSECL Output ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input Description Negative Supply Voltage. All VEE Pins Must be Externally Connected to Power Supply to Guarantee Proper Operation. Positive Supply Voltage. All VCC Pins Must be Externally Connected to Power Supply to Guarantee Proper Operation. LVCMOS Reference Voltage Output (VCC - VEE) / 2. ECL Reference Voltage Output Internal 50 W Termination Pin for CLK0. See Table 4. (Note 1) Noninverted Differential Input CLK0. Internal 75 kW to VEE. Internal 50 W Termination Pin for CLK0. See Table 4. (Note 1) Inverted Differential Input CLK0. Internal 75 kW to VEE and 36.5 kW to VCC. Internal 50 W Termination Pin 1. See Table 4. (Note 1) Noninverted Differential Input CLK1. Internal 75 kW to VEE. Internal 50 W Termination Pin for CLK1. See Table 4. (Note 1) Inverted Differential Input CLK1. Internal 75 kW to VEE and 36.5 kW to VCC. Noninverted Differential Outputs [0:9]. Typically Terminated with 50 W to VTT = VCC - 1.5 V Inverted Differential Outputs [0:9]. Typically Terminated with 50 W to VTT = VCC - 1.5 V Internal 50 W Termination Pin for SEL. See Table 4. (Note 1) Noninverted Differential Select Logic Input. Internal 75 kW to VEE. Internal 50 W Termination Pin for SEL. See Table 4. (Note 1) Inverted Differential Select Logic Input. Internal 75 kW to VEE and 36.5 kW to VCC. Internal 50 W Termination Pin for EN. See Table 4. (Note 1) Noninverted Differential Output Enable Pin. Internal 75 kW to VEE. Internal 50 W termination Pin for EN. See Table 4. (Note 1) Inverted Differential Output Enable Pin. Internal 75 kW to VEE and 36.5 kW to VCC. No Connect. The NC Pins are Electrically Connected to the Die and "MUST BE" Left Open.
1. In the differential configuration when the input termination pins (VTCLK, VTDCLK) are connected to a common termination voltage and if no signal is applied, then the device will be susceptible to self-oscillation.
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