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Details, datasheet, quote on part number:NBSG11BA
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| Part: | NBSG11BA |
| Category: | Timing Circuits => Clock Distribution |
| Description: | 2.5 V/3.3 V Sige 1:2 Differential Clock Driver With Rsecl Outputs , Package: Fcbga, Pins=16 |
| Company: | ON Semiconductor |
| Datasheet: | Download NBSG11BA datasheet File size : 83 kB |
| Request For quote: | Find where to buy NBSG11BA
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Datasheet text preview:
NBSG11 2.5V/3.3V SiGe 1:2 Differential Clock Driver with RSECL* Outputs
*Reduced Swing ECL
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The NBSG11 is a 1-to-2 differential fanout buffer, optimized for low skew and ultra-low JITTER. Inputs incorporate internal 50 W termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), CML, LVCMOS, LVTTL, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV.
MARKING DIAGRAM*
SG 11 LYW
· · · · ·
Maximum Input Clock Frequency up to 12 GHz Typical Maximum Input Data Rate up to 12 Gb/s Typical 30 ps Typical Rise and Fall Times 125 ps Typical Propagation Delay
FCBGA-16 BA SUFFIX CASE 489
RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V · RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V · RSECL Output Level (400 mV Peak-to-Peak Output), Differential Output Only · 50 W Internal Input Termination Resistors
QFN-16 MN SUFFIX CASE 485G
SG11 ALYW
· Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
A = Assembly Location L = Wafer Lot Y = Year W = Work Week *For further details, refer to Application Note AND8002/D
ORDERING INFORMATION
Device NBSG11BA NBSG11BAR2 Package 4x4 mm FCBGA-16 4x4 mm FCBGA-16 3x3 mm QFN-16 3x3 mm QFN-16 Shipping 100 Units / Tray 500 / Tape & Reel
NBSG11MN NBSG11MNR2
123 Units / Rail 3000 / Tape & Reel
Board NBSG11BAEVB
Description NBSG11BA Evaluation Board
© Semiconductor Components Industries, LLC, 2003
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April, 2003 - Rev. 6
Publication Order Number: NBSG11/D
NBSG11
1 A
VTCLK
2
NC
3
NC
4
Q1
VEE 16 VTCLK
NC 15
NC 14
VCC 13 Exposed Pad (EP)
1 2 NBSG11 3 4
12 11 10 9
Q0 Q0 Q1 Q1
B
CLK
VEE
VCC
Q1
CLK
Q0
C
CLK
VEE
VCC
CLK VTCLK
D
VTCLK
NC
NC
Q0
5 VEE
6 NC
7 NC
8 VCC
Figure 1. BGA-16 Pinout (Top View)
Figure 2. QFN-16 Pinout (Top View)
Table 1. Pin Description
Pin BGA D1 C1 QFN 1 2 Name VTCLK CLK I/O ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input RSECL Output RSECL Output RSECL Output RSECL Output Description Internal 50 W Termination Pin. See Table 2. Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to VCC.
B1
3
CLK
Noninverted Differential Input. Internal 75 kW to VEE.
A1 B2,C2 A2,A3,D2, D3 B3,C3 A4 B4 C4 D4 N/A
4 5,16 6,7,14,15 8,13 9 10 11 12 -
VTCLK VEE NC VCC Q1 Q1 Q0 Q0 EP
Internal 50 W Termination Pin. See Table 2. Negative Supply Voltage No Connect Positive Supply Voltage Inverted Differential Output 1. Typically Terminated with 50 W to VTT = VCC - 2 V Noninverted Differential Output 1. Typically Terminated with 50 W to VTT = VCC - 2 V Inverted Differential output 0. Typically Terminated with 50 W to VTT = VCC - 2 V Noninverted Differential Output 0. Typically Terminated with 50 W to VTT = VCC - 2 V Exposed Pad (Note 2)
1. The NC pins are electrically connected to the die and must be left open. 2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package bottom (see case drawing) must be attached to a heat-sinking conduit. 3. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self-oscillation.
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NBSG11
VCC VTCLK 36.5 KW 50 W CLK CLK 50 W VTCLK VEE 75 KW 75 KW Q0 Q0 Q1 Q1
Figure 3. Logic Diagram
Table 2. Interfacing Options
INTERFACING OPTIONS CML LVDS AC-COUPLED RSECL, PECL, NECL LVTTL, LVCMOS CONNECTIONS Connect VTCLK and VTCLK to VCC Connect VTCLK and VTCLK together Bias VTCLK and VTCLK Inputs within (VIHCMR) Common Mode Range Standard ECL Termination Techniques An external voltage should be be applied to the unused complementary differential input. Nominal voltage is 1.5 V for LVTTL and VCC/2 for LVCMOS inputs.
Table 3. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor (CLK, CLK) Internal Input Pullup Resistor (CLK) ESD Protection Moisture Sensitivity (Note 4) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 4. For additional information, see Application Note AND8003/D. Human Body Model Machine Model FCBGA-16 QFN-16 Oxygen Index: 28 to 34 Value 75 kW 36.5 kW > 2 kV > 100 V Level 3 Level 1 UL 94 V-0 @ 0.125 in 125
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