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Details, datasheet, quote on part number:NCN6004AFTBR2
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| Part: | NCN6004AFTBR2 |
| Category: | Interface and Interconnect => Smart Card Interface ICs |
| Description: | Dual Asynchronous/synchronous Smart Card Interface ic For Pos (Point of Sales), Atm, Pay TV, Package: 48 Leads, TQFP EP, Pins=0 |
| Company: | ON Semiconductor |
| Datasheet: | Download NCN6004AFTBR2 datasheet File size : 337 kB |
| Request For quote: | Find where to buy NCN6004AFTBR2
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Datasheet text preview:
NCN6004A Dual SAM/SIM Interface Integrated Circuit
The NCN6004A is an interface IC dedicated for Secured Access Module reader/writer applications. It allows the management of two e x t e r n a l ISO/EMV cards thanks to a simple and flexible microcontroller interface. Several NCN6004A interfaces can share a single data bus, assuming the external MPU provides the right Chip Select signals to identify each IC connected on the bus. A built in accurate protection system guarantees timely and controlled shutdown in the case of external error conditions. On top of that, the NCN6004A can independently handle the power supply, in the range 2.7 V to 5.0 V input voltage, provided to each external Smart Card. The interface monitors the current flowing into each Smart Card, a flag being set in the case of overload.
Features http://onsemi.com
TQFP48 CASE 932F PLASTIC
· Separated, Built-in DC/DC Converters Supply VCC Power to · · · · · · · · · · · · · · · · ·
External Cards 100% Compatible with ISO 7816-3, EMV and GIE-CB Standards Fully GSM Compliant Individually Programmable ISO/EMV Clock Generator Built-in Programmable CRD_CLK Stop Function Handles Run or High/Low State Programmable CRD_CLK Slopes to Cope with Wide Operating Frequency Range Programmable Independent VCC Supply for Each Smart Card Support up to 65 mA VCC Supply to Each ISO/EMV Card Multiple NCN6004A Parallel Operation on a Shared Bus 8 kV/Human Model ESD Protection on Each Interface Pin Provides C4/C8 Channels Provides 1.80 V, 3.0 V or 5.0 V Card Supply Voltages
MARKING DIAGRAM
NCN6004A AWLYYWW
48 1 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week
Typical Applications
Set Top Box Decoder ATM Multi Systems, POS, Handheld Terminals Internet E-commerce PC Interface Multiple Self Serve Automatic Machines Wireless Phone Payment Interface Automotive Operating Time Controller
ORDERING INFORMATION
Device NCN6004AFTBR2 Package TQFP48 Shipping 2000 Tape & Reel
© Semiconductor Components Industries, LLC, 2003
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June, 2003 - Rev. 2
Publication Order Number: NCN6004A/D
NCN6004A
CRD_DET_B MUX_MODE ANLG_GND ANLG_GND ANLG_VCC CRD_C8_B CRD_C4_B CRD_RST_B 38 CRD_IO_B 37 36 PWR_GND 35 L2b 34 L1b 33 PWR_VCC_B 32 CRD_VCC_B 31 CRD_CLK_B 30 CRD_CLK_A 29 CRD_VCC_A 28 PWR_VCC_A 27 L1a 26 L2a 25 PWR_GND 13 CLOCK_IN_A 14 ANLG_GND 15 CLOCK_IN_B 16 C8_B 17 C4_B 18 RESET_B 19 I/O_B 20 CRD_DET_A 21 CRD_C8_A 22 CRD_C4_A 23 CRD_RST_A 24 CRD_IO_A
EN_RPU
STATUS
INT
48 A0 A1 A2 A3 CARD_SEL PGM CS PWR_ON I/O_A 1 2 3 4 5 6 7 8 9
47 46
45
44
43
42
41
40
39
RESET_A 10 C4_A 11 C8_A 12
Figure 1. Pin Diagram
L2 J1 17 C3 41 10 mF 32 38 31 39 40 37 33 28 36 25 20 29 23 30 22 21 24 C1 10 mF VCC J2 17 C2 10 mF GND 1V CC RST 3 CLK 4 C4 2 GND VPP I/O C8 5 6 7 8 GND SMARTCARD # B DET DET 18 GND 1V CC 2 RST 3 CLK 4 C4 GND VPP I/O C8 5 6 7 8 GND SMARTCARD # A DET DET 18
L1
CHIP SELECT MPU BUS
MICRO CONTROLLER
VCC IRQ GND
1 2 3 4 5 6 7 8 44 45 46 47 9 10 11 12 13
27 22 mH 26 34 22 mH 35 L2a L1a L1b L2b A0 CRD_DET_B A1 CRD_VCC_B A2 A3 CRD_RST_B CARD_SEL CRD_CLK_B PGM CRD_C4_B CS PWR_ON CRD_C8_B MUX_MODE EN_RPU CRD_IO_B STATUS PWR_VCC_B INT I/O_A RESET_A C4_A C8_A CLK_IN_A ANLG_GND CLK_IN_B C8_B C4_B RESET_B I/O_B PWR_VCC_A NCN6004A PWR_GND PWR_GND CRD_DET_A CRD_VCC_A CRD_RST_A CRD_CLK_A CRD_C4_A CRD_C8_A CRD_IO_A ANLG_GND ANLG_VCC ANLG_GND
DATA PORT#B DATA PORT#A
GND
GND
14 15 16 17 18 19
42 VCC C4
43 48 100 nF GND
Figure 2. Typical Application http://onsemi.com
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NCN6004A
ANLG_VCC AGND
42 43 GND
INPUT VOLTAGE MONITOR 28 PWR_VCCA CARD#A DC/DC CONVERTER 27 L2a
INT STATUS
47 46
50 k 50 k 100 k VCC
VCC VCC
DET#A
INTERRUPT BLOCK
DET#B
26
L1a
29 CRD_VCCA 25 PWR_GND GND
CS PWR_ON A0 A1 A2 A3 CARD_SEL PGM CLK_INA
7 8 1 2 3 4 5 6 CLOCK#A DIVIDER CLK#A CNTL DIGITAL BLOCK
CARD#A SEQUENCER
CARD #A PINS DRIVERS
C8A C4A CLK_A RESET_A I/O#A
21 CRD_C8A 22 CRD_C4A 30 CRD_CLKA 24 CRD_IOA 23 CRD_RSTA
IO_A RST_A C4A C8A CONTROL
CLK#A DET#A
13
CARD#A DETECTION
20 CRD_DETA
CLK_INB
15
CLOCK#B DIVIDER CLK#B 26 k
DET#B
CARD#B DETECTION
41 CRD_DETB 40 CRD_C8B
CARD#B SEQUENCER
C8B C4B CLK_B RESET_A I/O#B
I/O_A RESET_A C4A
9 10 11
IO_B 100 k 100 k 100 k 26 k 100 k 100 k 100 k CNTL ANALOG & DIGITAL MULTIPLEX RST_B C4B C8B
CARD#B PINS DRIVERS
39 CRD_C4B 38 CRD_RSTB 37 CRD_IOB 31 CRD_CLKB
C8A 12 I/O_B RESET_B C4B C8B EN_RPU MUX_MODE 19 18 17 16 45
IO_A RST_A C4A C8A
CLK#B
CARD#B DC/DC CONVERTER
32 CRD_VCCB 36 PWR_GND GND 34 L2b
IO_B RST_B C4B C8B NOTE:
35
L1b
33 PWR_VCCB
44
An internal active pull down device forces all the smart card pins to zero when the chip is deactivated.
Figure 3. Block Diagram
http://onsemi.com
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