Part  NCP1207 
Category  
Description  PWM Currentmode Controller For Quasiresonant Operation 
Company  ON Semiconductor 
Datasheet  Download NCP1207 datasheet

Quote 
Features, Applications 
AND8112/D A QuasiResonant SPICE Model Eases Feedback Loop Designs Prepared by: Christophe Basso Prepared by: Joel Turchi ON Semiconductor http://onsemi.com Within the wide family of Switch Mode Power Supplies (SMPS), the Flyback converters represent the structure of choice for use in small and medium power applications. For compact designs and radiofrequency sensitive applications, e.g. TV sets or settop boxes, Quasi Resonant power supplies start to take a significant market share over the traditional fixed frequency topology. However, if the feedback loop control is well understood with this latter, for instance via a comprehensive literature and SPICE models, the situation differs for selfoscillating variable switching frequency structures where no model still exists. This article will show how a simple largesignal averaged SPICE model can be derived and used to ease the design work during stability analysis. QuasiResonant Operation It is difficult to abruptly dig into the analytical analysis without giving a basic idea of the operation of a converter working in QuasiResonance (QR). Figure 1 depicts a typical FLYBACK converter drainsource waveform as you probably have already observed. When the switch is closed, the drainsource voltage VDS is near 0 V and the input voltage Vg appears across the primary inductance LP: the current inside LP ramps up with a slope of Leakage Inductance Plateau: (Vout + Vf)/N Core is ResetWhen the controller instructs the switch opening, the drainsource quickly rises and the energy transfer between primary and secondary takes place: the secondary diode conducts and the output voltage flies back on the primary side, over LP. This "Flyback" plateau is equal (V + Vf) / N, where N is the secondary to primary turn ratio, V the output voltage and Vf the diode forward voltage drop. During this time, the primary current decreases with a slope now imposed by the reflected voltage Figure 2. The Primary Current Ramps Up and Down to Zero in DCMFigure 2 zooms on the simulated primary current (actually circulating in the magnetizing inductor), showing how it moves over one switching cycle. When the primary current reaches zero, the transformer core is fully demagnetized: we are in Discontinuous Conduction Mode (DCM). The primary inductance LP together with all the surrounding capacitive elements Ctot create a LC filter. When the secondary diode stops conducting = 0, the drain branch is left floating since the MOSFET is already open. As a result, a natural oscillation occurs, exhibiting the following frequency value: As in any sinusoidal signal, there are peaks and valleys. When you restart the switch in one valley, where the voltage is minimum, the MOSFET is no longer the seat of heavy turnon losses engendered by capacitive effects: this is the socalled QuasiResonance operation where the switching frequency depends on the peak current, the various slopes ON and OFF and the number of valleys you choose after the core reset. In our study, we will first concentrate on a simplified SPICE version where the power switch is actuated right after the reset detection point (parasitic ringings are neglected) and later on, a more sophisticated declination will incorporate parasitic delays. Modeling the Switch Network Figure 3 depicts a Flyback topology where the switching elements generating the above waveforms have been highlighted: the power switch (usually a MOSFET transistor) and a diode, performing a rectification job. During the converter operation, the Pulse Width Modulator controller (PWM) instructs the transistor to turn ON, in order to store energy in the primary side. The primary current builds up until the setpoint imposed by the feedback loop is reached. At this time, the controller toggles the transistor to the OFF state and energy transfers to the secondary side. If the ON and OFF states can be described by a set of linear equations, there exists a discontinuity linking these two events. Despite the presence of linear elements in the converter (capacitors, inductors and resistors), the presence of the commuting switch clearly introduces the nonlinearity that prevents us from directly writing the smallsignal equations... When learning electronic circuits at school, there were some exercises in which we were asked to reveal the transfer function of bipolar amplifiers. At that time, we learned to replace the transistor symbol by its equivalent smallsignal model: the schematic turned into the simple association of current and voltage sources that greatly simplified the analysis. In the average circuit modeling technique, we also follow the same philosophy: the exercise lies in isolating and replacing the switch network with a set of current and voltage sources whose electrical architecture do not vary with time. Therefore, plugging the equivalent model back into the converter of interest allows us to resolve its transfer characteristics. Deriving Equations The object of deriving a model consists in writing the equations that describe the switch network averaged input and output quantities that a) depend from each other b) obey to the control input. Let us draw the various waveforms before starting any line of algebra (Figure 4). From this picture, we can develop equations that will finally describe the averaged evolution of the values of interest, the input / output voltage and current of our switch network: where: V is the output voltage, Vg the input voltage, IP the primary peak current, N the / NP turn ratio and d the dutycycle = 1 d). Please note that in this first approach, we do not consider any delay occurring at the switch opening or induced by equation 3. These events will considered later on, in a more complex model. Figure 3. A Flyback Power Supply where Switches have been Isolated0Averaging Input / Output Voltages From the inductor voltsecond balance approximation, we know that the average voltage across an inductor operated in a steadystate converter is null. By looking at the V(LP) sketch, we obtain the following equation: t V(LP) u+ d(t) t Vg(t) u * d(t) t V(t) u + d(t) N t Vg(t) (1 * d(t)) N t V(t) u +0which lets us extract the classical output / input voltage ratio Now, by plugging equation 10 in equation 6, we obtain the average voltage across the primary switch terminal: <V1(t)> = t V(t) Vg(t) (1 * d(t)) + t V(t) Vg(t) u V(t) ut +t Vg(t) uwhich agrees with the inductor voltsecond balance approximation (from Figure 1 since, by definition, <V(LP)> = 0, then Vg appears across the switch terminals). To reveal <V2(t)>, let us plug equation 10 into <V2(t)> = [t V(t) Vg(t) u] d(t) + [t V(t) Vg(t) u] t V(t) u +t V(t) u t V(t) Vg(t) uwhich again could be deduced from Figure 3 since the average voltage across the secondary inductance is zero... Averaging Input / Output Currents The peak inductor current depends on the time during which Vg is applied over LP. If we recall that this time (actually ton d x TS, then: From Figure 4, the average current <I1(t)> can be obtained by evaluating the triangular area (charge in Coulomb) and dividing by the switching period. This is expressed by equation 4. Now plugging equation 4, we obtain: however, from equation 11, we know that <V1(t)> = <Vg(t)> thus equation 14 turns into:A 100% Efficiency Power Transfer... Assuming that 100% of the primary stored energy is released to the secondary side, then we can use equations 11 and 12 to write: Applying the same technique to the secondary current I2(t), leads to:From equation 15, we can see that a current is generated by a voltage multiplied by a term. This term is obviously homogenous to the inverse of an impedance. By rearranging equation 15, we obtain: 
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2SC2922 : . Silicon NPN Epitaxial Planar Transistor (Complement to type 2SA1216) sAbsolute maximum ratings (Ta=25°C) Symbol VCBO VCEO VEBO PC Tj Tstg to +150 Unit °C Symbol ICBO IEBO V(BR)CEO hFE VCE(sat) fT COB Conditions VCB=10V, f=1MHz . FFM104 : Fast Recovery Type. Plastic package has Underwriters Laboratory Flammability Classification 94VO Utilizing Flame Retardant Epoxy M olding Compound. For surface mounted applications. Exceeds environmental standards / 228 Low leakage current. Case : Molded plastic, JEDE C DO214AC Terminals : Solder plated, s olderable per MILSTD750, Method 2026 Polarity : Indicated by cathode. SN74AHC1GU04DBV : Single Inverter Gate. EPIC TM (EnhancedPerformance Implanted CMOS) Process Operating Range to 5.5V VCC Unbuffered Output LatchUp Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MILSTD883, Method 3015; Exceeds 200 V Using Machine Model = 200 pF, = 0) Package Options Include Plastic SmallOutline Transistor (DBV, DCK) Packages The SN74AHC1GU04. TLP174GA : Pin = 4 ;; Package = Sop ;; Load Voltage Voff (Min.) = 400 (V) ;; Load Current Ion (Max.) = 0.12 (A) ;; On Resistance Ron (Max.) = 35 (Ohm) ;; On Resistance Ron (Typ.) = 17 (Ohm) ;; Output Capacitance Coff (Typ.) = 70 (pF) ;; ISOlation Voltage BVS (Min.) = 1500 (V) ;; = 1 Form A, Current Limit Function. Z8F011A : 8bit microcontrollers with eXtended Peripherals.. ZiLOG Worldwide Headquarters 532 Race Street San Jose, CA 951263432 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters 532 Race Street San Jose, CA 951263432 Telephone:. UC2854AJ : Advanced Highpower Factor Preregulator. Factor Limits Line Current Distortion < 3% WorldWide Operation Without Switches Accurate Power Limiting FixedFrequency Average CurrentMode Control High Bandwidth (5 MHz), LowOffset Current Amplifier Integrated Current and Voltage Amplifier Output Clamps Multiplier Improvements: Linearity, 500 mV VAC Offset (Eliminates External Resistor), 5 V Multout. IT415HA : Isotab Triacs Electrically Isolated. CY4D : Quartz Crystal Leaded HC49 Crystal. Part number CY48A CY100A Freq. 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OSTHB183180 : Through Hole Terminal Block  Wire To Board Connectors, Interconnect Through Hole; CONN TERM BLOCK 18POS 3.81MM. s: Color: Gray ; Current: 10A ; : Interlocking (Side) ; Mating Orientation: Horizontal with Board ; Mounting Type: Through Hole ; Pitch: 0.150" (3.81mm) ; Voltage: 300V ; Wire Gauge: 1620 AWG ; Number of Levels: 1 ; Positions Per Level:. MAAM011122 : MACOM Technology Solutions Extends CATV Portfolio with Highly Linear Variable Gain Amplifier at ANGACOM 2013 Exhibition and Congress. The MAAM011122 is an integrated two stage differential variable gain amplifier designed specifically for CATV headend, and system amplifier infrastructure reverse path applications. This multichip module VGA leverages. PQ17C : 250 MHz  500 MHz, 360 deg RF/MICROWAVE PHASE SHIFTER. s: Frequency Range: 250 to 500 MHz ; Phase Shift Range: 360deg, 1 ; Insertion Loss: 4.5 dB ; Input VSWR: 2 1 ; Package Type: HERMETIC SEALED, CASE PQ. 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