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Part: NCP1570DR2
Category:
Power Management
-> DC-DC Converters
-> DC-DC Switching
-> Controllers
Description: Low Voltage Synchronous Buck Controller, Package: Soic, Pins=8
Company: ON Semiconductor
Datasheet: Download NCP1570DR2 datasheet File size : 161 kB
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Datasheet text preview:
NCP1570 Low Voltage Synchronous Buck Controller
The NCP1570 is a low voltage buck controller. It provides the control for a DCDC power solution producing an output voltage as low as 0.985 V over a wide current range. The NCP1570based solution is powered from 12 V with the output derived from a 5 V supply. It contains all required circuitry for a synchronous NFET buck regulator using the V2TM control method to achieve the fastest possible transient response and best overall regulation. The NCP1570 operates at a fixed internal 200 kHz frequency and is packaged in an SO8. The NCP1570 provides undervoltage lockout protection, Soft Start, Power Good with delay, and builtin adaptive nonoverlap.
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8 1 SO8 D SUFFIX CASE 751
· · · · · · · · · · · · · ·
Features 0.985 V ± 1.0% Reference V2 Control Topology 200 ns Transient Response Programmable Soft Start Power Good Programmable Power Good Delay 40 ns Gate Rise and Fall Times (3.3 nF Load) 50 ns Adaptive FET NonOverlap Time Fixed 200 kHz Oscillator Frequency Undervoltage Lockout On/Off Control Through Use of the COMP Pin Overvoltage Protection through Synchronous MOSFETs Synchronous NChannel Buck Design Dual Supply, 12 V Control, 5 V Power Source
PIN CONNECTIONS AND MARKING DIAGRAM
VCC PWRGD PGDELAY COMP A WL, L YY, Y WW, W 1 1570 ALYW 8 GND VFB GATE(L) GATE(H) = Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device NCP1570D NCP1570DR2 Package SO8 SO8 Shipping 98 Units/Rail 2500 Tape & Reel
© Semiconductor Components Industries, LLC, 2002
1
February, 2002 Rev. 4
Publication Order Number NCP1570/D
NCP1570
12 V PWRGD VLOGIC R1 50 k C4 0.1 µF VCC PWRGD NCP1570 PGDELAY COMP C13 0.1 µF GND VFB 100 pF C6 NTD4302 Q2 NTD4302 Q1 1.2 µH L1
+ + + +
GND
5.0 V 33 µF/8.0 V/1.6 Arms × 4 C1
+ +
C2
+
C3
1.2 V/10 A
1.2 V
GATE(L) GATE(H)
2.0 k R3
C8
C9
C10
C11 GND
C12 0.01 µF
R5 10 k
56 µF/4.0 V/1.6 Arms SPCAP 40 m
Figure 1. Applications Circuit MAXIMUM RATINGS*
Rating Operating Junction Temperature Storage Temperature Range ESD Susceptibility (Human Body Model) ESD Susceptibility (Machine Model) Lead Temperature Soldering: Moisture Sensitivity Level Package Thermal Resistance, SO8 JunctiontoCase, RJC JunctiontoAmbient, RJA 1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed. Reflow: (Note 1) Value 150 65 to 150 2.0 200 230 peak 2 48 165 Unit °C °C kV V °C °C/W °C/W
MAXIMUM RATINGS
Pin Name IC Power Input Compensation Capacitor Voltage Feedback Input Power Good Output Power Good Delay HighSide FET Driver LowSide FET Driver Ground Pin Symbol VCC COMP VFB PWRGD PGDELAY GATE(H) GATE(L) GND VMAX 15 V 6.0 V 6.0 V 15 V 6.0 V 15 V 15 V 0.5 V VMIN 0.5 V 0.5 V 0.5 V 0.5 V 0.5 V 0.5 V 2.0 V for 50 ns 0.5 V 2.0 V for 50 ns 0.5 V ISOURCE N/A 10 mA 1.0 mA 1.0 mA 1.0 mA 1.5 A Peak 200 mA DC 1.5 A Peak 200 mA DC 1.5 A Peak 450 mA DC ISINK 1.5 A Peak 450 mA DC 10 mA 1.0 mA 20 mA 10 mA 1.5 A Peak 200 mA DC 1.5 A Peak 200 mA DC N/A
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2
NCP1570
ELECTRICAL CHARACTERISTICS (0°C < TJ < 125°C, 11.4 V < VCC < 12.6 V, CGATE(H) = CGATE(L) = 3.3 nF, CPGDELAY = 0.01 µF, CCOMP = 0.1 µF; unless otherwise specified.)
Characteristic Error Amplifier VFB Bias Current COMP Source Current COMP Sink Current Reference Voltage COMP Max Voltage COMP Min Voltage COMP Fault Discharge Current at UVLO COMP Fault Discharge Threshold to Reset UVLO Open Loop Gain Unity Gain Bandwidth PSRR @ 1.0 kHz Output Transconductance Output Impedance GATE(H) and GATE(L) Rise Time Fall Time GATE(H) to GATE(L) Delay GATE(L) to GATE(H) Delay Minimum Pulse Width High Voltage (AC) 1.0 V 2.0 V GATE(L) 2.0 V GATE(X) = 4.0 V Measure GATE(L) or GATE(H) 0.5 nF < CGATE(H) = CGATE(L) < 10 nF Note 2 Measure GATE(L) or GATE(H) 0.5 nF < CGATE(H) = CGATE(L) < 10 nF Note 2 Resistance to GND. Note 2 25 25 VCC 0.5 40 40 50 50 250 VCC 80 80 75 75 ns ns ns ns ns V VFB = 0 V COMP = 1.5 V, VFB = 0.8 V COMP = 1.5 V, VFB = 1.2 V COMP = VFB VFB = 0.8 V VFB = 1.2 V COMP = 1.2 V, VCC = 6.9 V COMP = 0.5 V, VCC = 12 V 6.9 V 12 V. Ramp COMP to 0.1 V. Monitor I (COMP) 15 15 0.975 2.4 0.5 0.1 0.2 30 30 0.985 2.7 0.1 1.7 0.25 98 20 70 32 2.5 2.0 60 60 0.995 0.2 0.3 µA µA µA V V V mA V dB kHz dB mmho M Test Conditions Min Typ Max Unit
Low Voltage (AC)
0
0.5
V
GATE(H)/(L) PullDown Power Good Lower Threshold, VO Rising Lower Threshold, VO Falling PWRGD Low Voltage Delay Charge Current Delay Clamp Voltage Delay Charge Threshold Delay Discharge Current at UVLO Delay Discharge Threshold to Reset UVLO "Good" Signal Delay
20
50
115
k
ISINK = 1.0 mA, VFB = 0 V PGDELAY = 2.0 V Ramp PGDELAY, Monitor PWRGD PGDELAY = 0.5 V, VCC = 6.9 V PGDELAY = 0.5 V, VCC = 12 V to 6.9 V to 12 V, Ramp PGDELAY to 0.1 V, Monitor I (PGDELAY) With 0.01 µF. Note 2
0.856 0.666 7.0 3.45 3.1 0.5 0.1
0.887 0.690 0.15 12 4.0 3.3 2.0 0.25
0.917 0.713 0.4 18 4.3 3.5 0.3
V V V µA V V mA V
1.0
3.0
5.0
ms
2. Guaranteed by design. Not tested in production.
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3
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