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Part: NCP1571
Category:
Description: Low Voltage Synchronous Buck Controller
Company: ON Semiconductor
Datasheet: Download NCP1571 datasheet File size : 161 kB
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AND8079/D A Low Cost DDR Memory Power Supply Using the NCP1571 Synchronous Buck Converter and a LM358 Based Linear Voltage Regulator
Prepared by: Jim Lepkowski Senior Application Engineer
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APPLICATION NOTE
INTRODUCTION This application note describes a low cost power supply circuit for a DDR (Double Data Rate) memory system. The design is based on the NCP1570/NCP1571 low voltage synchronous buck converter. The reference design created to evaluate the system uses a 3.80 by 2.15 two layer printed circuit board, optimized for a small solution size at an economical cost. DDR memories bring new challenges to the power supply by requiring an efficient main power of 2.5 V (Vdd) and a second voltage (Vtt) that accurately tracks one half of Vdd (i.e. 1.25 V) that is capable of both sourcing and sinking current. In addition, a third voltage is required (VREF) that also tracks Vdd/2. A low voltage synchronous buck converter is used to create an 8.0 A output at 2.5 V, while the Vtt and VREF voltages are created using a unique operational amplifier linear regulator circuit. The demonstration circuit is designed for low power DDR systems such as desktop PCs, but the circuit's output power capability can be increased with the selection of the external inductor and capacitors for high power systems such as PC workstations. DDR Memory Power Supply Requirements Figure 1 shows a simplified schematic of the DDR memory system. Voltage Vdd powers the memory ICs, in addition to the buffer interface circuits. The termination voltage Vtt is used for the pull-up resistors and must be able to either sink or source current. For example, if all of the driver circuits are at a logic high state (i.e. VOH = Vdd = 2.5 V), the Vtt supply will have to sink current in order to maintain its 1.25 V. In contrast, if all of the driver circuits are at a logic low state (i.e. VOL = Vss = 0 V), the Vtt supply will have to source current because the termination resistors will be effectively connected to ground.
Vdd
Vtt = Vdd/2 RT 25 Receiver
RS Transmitter 22
VREF
Figure 1. DDR Memory Simplified Schematic
Vtt is equal to Vdd/2 instead of Vdd in order to save power. The power dissipated in the resistors is equal to voltage squared divided by the bus resistance, thus a termination voltage of Vdd/2 provides a factor of four power savings. The third voltage is used as a reference voltage to the differential amplifier input section of the receiver ICs. A summary of the specifications for the DDR memory system is listed below. The transient requirements are not defined in the industry JEDEC standards.
DDR Voltage Vdd Vtt Output Voltage 2.5 V Vdd/2 (^1.25 V) Vdd/2
Tolerance "200 mV Vdd/2 " 3% (1.250 V " 37.5 mV) Vtt " 40 mV
Output Current 8.0 A "2.0 A (Sink and Source) 5.0 mA
VREF
© Semiconductor Components Industries, LLC, 2002
1
October, 2002 - Rev. 1
Publication Order Number: AND8079/D
AND8079/D
Many industry experts have predicted that DDR memory will soon become the standard for desktop computers, with notebooks shortly behind. Next generation DDR-II generation systems are likely to have a lower Vdd voltage of 1.8 V with a Vtt and VREF voltage equal to 900 mV. This lower voltage will be required to satisfy the consumer's requirement for more memory without a large increase in required power. Supply Voltage (Vdd) The Vdd 2.5 V power supply is created with the NCP1571 low voltage synchronous buck controller. The NCP1571 controller contains the required circuitry for a synchronous N-channel MOSFET buck regulator. The V2t control method is used to achieve a fast 200 ns transient response and an output regulation of ±1.0%. The IC operates at a fixed internal frequency of 200 kHz. In addition, the NCP1571 provides the following features: undervoltage lockout protection, programmable soft start, power good signal with delay and overvoltage protection. Note the NCP1570 and NCP1571 are functionally and pin for pin equivalent. The NCP1571's under voltage lockout operation (UVLO) feature has been modified for applications that require a parallel standby power supply in addition to the main power supplied by the buck converter. Termination Supply Voltage (Vtt) and Reference Voltage (VREF) The Vtt supply voltage is equal to one half of the Vdd voltage, or approximately 1.25 V. Operational amplifiers U2A and U2B function as voltage followers to create the Vtt voltage. The input to U2B is created by the resistive voltage divider formed by R5 and R6 and divides the 2.5 V Vdd supply by two to form the VREF reference voltage. Also, U2B provides filtering to remove any of the high frequency switching noise that is results from the synchronous buck converter. The Vtt output of the circuit formed by U2A and transistors Q4 and Q5 tracks the voltage at the non-inverting terminal by virtue of the voltage follower circuit configuration. Thus, the output of voltage of the Vtt supply is referenced to 50% of the 2.5 V Vdd supply, rather than an absolute 1.25 V reference. The sink and source ability of the Vtt supply is provided by MOSFETs Q4 and Q5 which are used to extend the current capability of the operational amplifier circuit. When the Vtt supply is in the current sinking mode of operation, Q4 is "OFF" and Q5 is "ON". The output of U2A will be at a negative voltage (i.e. 5.0 V) to control the Vgs of the P-channel MOSFET (Q5) in order to maintain the Vtt voltage of 1.25 V. In a similar manner, when the Vtt supply is in the current sourcing mode of operation, Q4 is "ON" and Q5 is "OFF". The output of U2A will reach a positive voltage (i.e. + 4.5 V) to control the Vgs of the N-channel MOSFET (Q5) in order to maintain the Vtt voltage of 1.25 V. Resistor R7 is used to isolate the output of U2B from Vtt and the bulk capacitor C20. The slew rate of the operational amplifier and the ability of the bulk capacitors to hold the voltage at 1.25 V under the load conditions control the transient response of the Vtt control loop. Note that the bulk capacitors maintain the Vtt voltage at approximately 1.25 V; therefore, the operational amplifier is only required to slew its output a relatively small amount; therefore, the relatively slow slew rate of the LM358 operational amplifiers is not a limiting factor in the design. Standby Power Operation The demonstration PCB has the provision of providing a low power standby mode of operation to the DDR memory system. This mode could be used to provide a 2.5 V low current standby voltage to the memory ICs when the main 5.0 V input power is not available. A MC33375 (U3) 300 mA low dropout voltage regulator (LDO) was chosen for the design to provide the 2.5 V standby power. The MC33375 has an ON/OFF enable pin and is available in a SOT-223 package. The performance of the standby regulator was not verified. Q1, a N-Channel MOSFET, serves as a diode to prevent current flow back to the main 5.0 volt input power supply during the standby mode. The MOSFET was chosen instead of a Schottky diode in order to minimize the voltage drop and power consumption of the diode.
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Q1 MTB1306 D2 PAK L1 TP5 5 V_Input C1 1800mF 10V C2 1800mF 10V C3 1800mF 10V C4 0.1mF C5 1800mF 10V Prov. 1 mH Q2 MTB1306 D2 PAK L2 2.2mH D1 MBRM110LT PowerMite Prov. Q3 R1 10 1 TP8 V_Logic C12 0.1mF R2 47k C13 0.01mF 2 3 4 PWRGD PGDELAY COMP C14 0.1mF MC33375ST-2.5T3 SOT-223 U3 Prov. TP9 V_5P0_STBV 1 VIN 2 C24 1 mF ON OFF VOUT 3 GND 4 U2A LM358 Micro8 4 2 3 NCP1571 SO-8 8 GND Vfb GATE(L) GATE(H) 7 6 5 C6 100pF C16 VTT (+1.25V, 2A) TP2 1.25V_Vtt Q4 NTD4302 D2 PAK
To = 1.0%
4
TP6 GND_Input TP7 12 V_Input
R3 20k R4 13k
TP1 2.5V C7 1800mF 6.3V Prov. C8 C9 1800mF 0.1mF 6.3V C11 C10 1800mF 1800mF 6.3V 6.3V VDDQ (+2.5V, 8A)
Tol = 1.0%
U1 VCC
MTB1306 D2PAK
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AND8079/D
3
-
V- 0.1mF 1 OUT V+ 8 C17
R7 1k C20 1800mF 6.3V Prov. C21 C22 1800mF 0.1mF 6.3V Prov. C23 1800mF 6.3V
+
TP3 GND_Output
0.1mF
Q5 MTD20P03HDL DPAK
C18 TP10 -12 V_Input Tol. = 1.0% R5 10K U2B LM358 6 0.15mF
VREF (+1.25V, 2mA)
TP4 1.25V_Ref
-
OUT
7
R8 200
+
5 Tol. = 1.0% R6 10K C15 1 mF
R9 100
C19 2 mF
Note: The provisional components were not used in the verification of the reference design.
Figure 2. DDR Memory Reference Design
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